[PATCH 2/9] powerpc: dts: p2020: Make PCIe nodes compatible for Linux kernel driver

[Pali Rohár]

Linux P2020 PCIe kernel driver uses compatible string fsl,mpc8548-pcie and
needs more DT properties. Copy P2020 PCIe nodes and definitions from
upstream Linux kernel.

Signed-off-by: Pali Rohár <pali at kernel.org>
---
 arch/powerpc/dts/p2020-post.dtsi | 65 ++++++++++++++++++++++++++++++--
 1 file changed, 62 insertions(+), 3 deletions(-)

diff --git a/arch/powerpc/dts/p2020-post.dtsi b/arch/powerpc/dts/p2020-post.dtsi
index 804db73c3777..6eb6fedd4156 100644
--- a/arch/powerpc/dts/p2020-post.dtsi
+++ b/arch/powerpc/dts/p2020-post.dtsi
@@ -59,32 +59,91 @@
 
 /* PCIe controller base address 0x8000 */
 &pci2 {
-	compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
+	compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq", "fsl,mpc8548-pcie";
 	law_trgt_if = <0>;
 	#address-cells = <3>;
 	#size-cells = <2>;
 	device_type = "pci";
 	bus-range = <0x0 0xff>;
+	clock-frequency = <33333333>;
+	interrupts = <24 2 0 0>;
+
+	pcie at 0 {
+		reg = <0 0 0 0 0>;
+		#interrupt-cells = <1>;
+		#size-cells = <2>;
+		#address-cells = <3>;
+		device_type = "pci";
+		interrupts = <24 2 0 0>;
+		interrupt-map-mask = <0xf800 0 0 7>;
+
+		interrupt-map = <
+			/* IDSEL 0x0 */
+			0000 0x0 0x0 0x1 &mpic 0x8 0x1 0x0 0x0
+			0000 0x0 0x0 0x2 &mpic 0x9 0x1 0x0 0x0
+			0000 0x0 0x0 0x3 &mpic 0xa 0x1 0x0 0x0
+			0000 0x0 0x0 0x4 &mpic 0xb 0x1 0x0 0x0
+			>;
+	};
 };
 
 /* PCIe controller base address 0x9000 */
 &pci1 {
-	compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
+	compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq", "fsl,mpc8548-pcie";
 	law_trgt_if = <1>;
 	#address-cells = <3>;
 	#size-cells = <2>;
 	device_type = "pci";
 	bus-range = <0x0 0xff>;
+	clock-frequency = <33333333>;
+	interrupts = <25 2 0 0>;
+
+	pcie at 0 {
+		reg = <0 0 0 0 0>;
+		#interrupt-cells = <1>;
+		#size-cells = <2>;
+		#address-cells = <3>;
+		device_type = "pci";
+		interrupts = <25 2 0 0>;
+		interrupt-map-mask = <0xf800 0 0 7>;
+
+		interrupt-map = <
+			/* IDSEL 0x0 */
+			0000 0x0 0x0 0x1 &mpic 0x4 0x1 0x0 0x0
+			0000 0x0 0x0 0x2 &mpic 0x5 0x1 0x0 0x0
+			0000 0x0 0x0 0x3 &mpic 0x6 0x1 0x0 0x0
+			0000 0x0 0x0 0x4 &mpic 0x7 0x1 0x0 0x0
+			>;
+	};
 };
 
 /* PCIe controller base address 0xa000 */
 &pci0 {
-	compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
+	compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq", "fsl,mpc8548-pcie";
 	law_trgt_if = <2>;
 	#address-cells = <3>;
 	#size-cells = <2>;
 	device_type = "pci";
 	bus-range = <0x0 0xff>;
+	clock-frequency = <33333333>;
+	interrupts = <26 2 0 0>;
+
+	pcie at 0 {
+		reg = <0 0 0 0 0>;
+		#interrupt-cells = <1>;
+		#size-cells = <2>;
+		#address-cells = <3>;
+		device_type = "pci";
+		interrupts = <26 2 0 0>;
+		interrupt-map-mask = <0xf800 0 0 7>;
+		interrupt-map = <
+			/* IDSEL 0x0 */
+			0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0
+			0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0
+			0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0
+			0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0
+			>;
+	};
 };
 
 &lbc {
-- 
2.20.1