[PATCH v2] ARM: dts: imx: Add support for Data Modul i.MX8M Mini eDM SBC
Stefano Babic
sbabic at denx.de
Mon Apr 11 18:12:10 CEST 2022
Hi Marek,
I get error from CI due to CONFIG_ that should be in
configs/imx8mm_data_modul_edm_sbc_defconfig (also, Kbuild) and are
defined in include. I can recognize:
#define CONFIG_SYS_I2C_SPEED 100000
in include/configs/imx8mm_data_modul_edm_sbc.h, but it is not the only
case (dropping it I get the same error). You see here:
https://source.denx.de/u-boot/custodians/u-boot-imx/-/jobs/420924
Can you check and repost ?
Best regards,
Stefano
On 31.03.22 00:09, Marek Vasut wrote:
> Add support for Data Modul i.MX8M Mini eDM SBC board. This is an
> evaluation board for various custom display units. Currently
> supported are serial console, ethernet, eMMC, SD, SPI NOR,
> USB host and USB OTG.
>
> Reviewed-by: Fabio Estevam <festevam at denx.de>
> Signed-off-by: Marek Vasut <marex at denx.de>
> Cc: Fabio Estevam <festevam at gmail.com>
> Cc: Peng Fan <peng.fan at nxp.com>
> Cc: Stefano Babic <sbabic at denx.de>
> ---
> V2: - Disable UHS mode support in SPL, the overhead incured by bringing up UHS
> mode in SPL does not make sense for loading less than 1 MiB u-boot.itb.
> - Select primary boot device based on boot device indicated by BootROM,
> either eMMC or SD boot device is supported. Always select the other
> boot device, SD or eMMC, as fallback boot device.
> - Set 'devnum' environment variable based on boot device indicated by BootROM
> unless the 'devnum' variable is already set. This way it is possible to boot
> from the same boot media from which BootROM started U-Boot SPL and U-Boot SPL
> started U-Boot itself.
> - Add RB from Fabio
> ---
> arch/arm/dts/Makefile | 1 +
> .../dts/imx8mm-data-modul-edm-sbc-u-boot.dtsi | 116 ++
> arch/arm/dts/imx8mm-data-modul-edm-sbc.dts | 996 +++++++++
> arch/arm/mach-imx/imx8m/Kconfig | 8 +
> board/data_modul/imx8mm_edm_sbc/Kconfig | 12 +
> board/data_modul/imx8mm_edm_sbc/MAINTAINERS | 8 +
> board/data_modul/imx8mm_edm_sbc/Makefile | 13 +
> board/data_modul/imx8mm_edm_sbc/common.c | 37 +
> .../imx8mm_data_modul_edm_sbc.c | 110 +
> board/data_modul/imx8mm_edm_sbc/imximage.cfg | 8 +
> .../data_modul/imx8mm_edm_sbc/lpddr4_timing.h | 14 +
> .../imx8mm_edm_sbc/lpddr4_timing_2G_32.c | 1845 +++++++++++++++++
> .../imx8mm_edm_sbc/lpddr4_timing_4G_32.c | 1842 ++++++++++++++++
> board/data_modul/imx8mm_edm_sbc/spl.c | 179 ++
> configs/imx8mm_data_modul_edm_sbc_defconfig | 229 ++
> include/configs/imx8mm_data_modul_edm_sbc.h | 133 ++
> 16 files changed, 5551 insertions(+)
> create mode 100644 arch/arm/dts/imx8mm-data-modul-edm-sbc-u-boot.dtsi
> create mode 100644 arch/arm/dts/imx8mm-data-modul-edm-sbc.dts
> create mode 100644 board/data_modul/imx8mm_edm_sbc/Kconfig
> create mode 100644 board/data_modul/imx8mm_edm_sbc/MAINTAINERS
> create mode 100644 board/data_modul/imx8mm_edm_sbc/Makefile
> create mode 100644 board/data_modul/imx8mm_edm_sbc/common.c
> create mode 100644 board/data_modul/imx8mm_edm_sbc/imx8mm_data_modul_edm_sbc.c
> create mode 100644 board/data_modul/imx8mm_edm_sbc/imximage.cfg
> create mode 100644 board/data_modul/imx8mm_edm_sbc/lpddr4_timing.h
> create mode 100644 board/data_modul/imx8mm_edm_sbc/lpddr4_timing_2G_32.c
> create mode 100644 board/data_modul/imx8mm_edm_sbc/lpddr4_timing_4G_32.c
> create mode 100644 board/data_modul/imx8mm_edm_sbc/spl.c
> create mode 100644 configs/imx8mm_data_modul_edm_sbc_defconfig
> create mode 100644 include/configs/imx8mm_data_modul_edm_sbc.h
>
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index 644ba961a22..244386a9d14 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -899,6 +899,7 @@ dtb-$(CONFIG_ARCH_IMX8ULP) += \
> imx8ulp-evk.dtb
>
> dtb-$(CONFIG_ARCH_IMX8M) += \
> + imx8mm-data-modul-edm-sbc.dtb \
> imx8mm-evk.dtb \
> imx8mm-icore-mx8mm-ctouch2.dtb \
> imx8mm-icore-mx8mm-edimm2.2.dtb \
> diff --git a/arch/arm/dts/imx8mm-data-modul-edm-sbc-u-boot.dtsi b/arch/arm/dts/imx8mm-data-modul-edm-sbc-u-boot.dtsi
> new file mode 100644
> index 00000000000..184c30ab4a7
> --- /dev/null
> +++ b/arch/arm/dts/imx8mm-data-modul-edm-sbc-u-boot.dtsi
> @@ -0,0 +1,116 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2022 Marek Vasut <marex at denx.de>
> + */
> +
> +#include "imx8mm-u-boot.dtsi"
> +
> +/ {
> + aliases {
> + eeprom0 = &eeprom;
> + mmc0 = &usdhc3; /* eMMC */
> + mmc1 = &usdhc2; /* MicroSD */
> + };
> +
> + config {
> + dmo,ram-coding-gpios = <&gpio2 8 0>, <&gpio2 1 0>, <&gpio2 0 0>;
> + };
> +
> + wdt-reboot {
> + compatible = "wdt-reboot";
> + wdt = <&wdog1>;
> + u-boot,dm-spl;
> + };
> +};
> +
> +&buck4_reg {
> + u-boot,dm-spl;
> +};
> +
> +&buck5_reg {
> + u-boot,dm-spl;
> +};
> +
> +&i2c1 {
> + u-boot,dm-spl;
> +};
> +
> +&pinctrl_hog_sbc {
> + u-boot,dm-spl;
> +};
> +
> +&pinctrl_i2c1 {
> + u-boot,dm-spl;
> +};
> +
> +&pinctrl_i2c1_gpio {
> + u-boot,dm-spl;
> +};
> +
> +&pinctrl_pmic {
> + u-boot,dm-spl;
> +};
> +
> +&pinctrl_uart3 {
> + u-boot,dm-spl;
> +};
> +
> +&pinctrl_usdhc2 {
> + u-boot,dm-spl;
> +};
> +
> +&pinctrl_usdhc3 {
> + u-boot,dm-spl;
> +};
> +
> +&pmic {
> + u-boot,dm-spl;
> +
> + regulators {
> + u-boot,dm-spl;
> + };
> +};
> +
> +&gpio1 {
> + u-boot,dm-spl;
> +};
> +
> +&gpio2 {
> + u-boot,dm-spl;
> +};
> +
> +&gpio3 {
> + u-boot,dm-spl;
> +};
> +
> +&gpio4 {
> + u-boot,dm-spl;
> +};
> +
> +&gpio5 {
> + u-boot,dm-spl;
> +};
> +
> +&uart3 {
> + u-boot,dm-spl;
> +};
> +
> +&usbotg1 {
> + dr_mode = "peripheral";
> +};
> +
> +&usdhc2 {
> + u-boot,dm-spl;
> + sd-uhs-sdr104;
> + sd-uhs-ddr50;
> +};
> +
> +&usdhc3 {
> + u-boot,dm-spl;
> + mmc-hs400-1_8v;
> + mmc-hs400-enhanced-strobe;
> +};
> +
> +&wdog1 {
> + u-boot,dm-spl;
> +};
> diff --git a/arch/arm/dts/imx8mm-data-modul-edm-sbc.dts b/arch/arm/dts/imx8mm-data-modul-edm-sbc.dts
> new file mode 100644
> index 00000000000..154116d01c9
> --- /dev/null
> +++ b/arch/arm/dts/imx8mm-data-modul-edm-sbc.dts
> @@ -0,0 +1,996 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright 2022 Marek Vasut <marex at denx.de>
> + */
> +
> +/dts-v1/;
> +
> +#include <dt-bindings/net/qca-ar803x.h>
> +#include <dt-bindings/phy/phy-imx8-pcie.h>
> +#include "imx8mm.dtsi"
> +
> +/ {
> + model = "Data Modul i.MX8M Mini eDM SBC";
> + compatible = "dmo,imx8mm-data-modul-edm-sbc", "fsl,imx8mm";
> +
> + aliases {
> + rtc0 = &rtc;
> + rtc1 = &snvs_rtc;
> + };
> +
> + chosen {
> + stdout-path = &uart3;
> + };
> +
> + memory at 40000000 {
> + device_type = "memory";
> + /* There are 1/2/4 GiB options, adjusted by bootloader. */
> + reg = <0x0 0x40000000 0 0x40000000>;
> + };
> +
> + backlight: backlight {
> + compatible = "pwm-backlight";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_panel_backlight>;
> + brightness-levels = <0 1 10 20 30 40 50 60 70 75 80 90 100>;
> + default-brightness-level = <7>;
> + enable-gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>;
> + pwms = <&pwm1 0 5000000>;
> + /* Disabled by default, unless display board plugged in. */
> + status = "disabled";
> + };
> +
> + clk_xtal25: clk-xtal25 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <25000000>;
> + };
> +
> + panel: panel {
> + backlight = <&backlight>;
> + power-supply = <®_panel_vcc>;
> + /* Disabled by default, unless display board plugged in. */
> + status = "disabled";
> + };
> +
> + reg_panel_vcc: regulator-panel-vcc {
> + compatible = "regulator-fixed";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_panel_vcc_reg>;
> + regulator-name = "PANEL_VCC";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + gpio = <&gpio3 6 0>;
> + enable-active-high;
> + /* Disabled by default, unless display board plugged in. */
> + status = "disabled";
> + };
> +
> + reg_usdhc2_vcc: regulator-usdhc2-vcc {
> + compatible = "regulator-fixed";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_usdhc2_vcc_reg>;
> + regulator-name = "V_3V3_SD";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + gpio = <&gpio2 19 0>;
> + enable-active-high;
> + };
> +
> + watchdog-gpio {
> + /* TPS3813 */
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_watchdog_gpio>;
> + compatible = "linux,wdt-gpio";
> + always-enabled;
> + gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
> + hw_algo = "level";
> + /* Reset triggers in 2..3 seconds */
> + hw_margin_ms = <1500>;
> + /* Disabled by default */
> + status = "disabled";
> + };
> +};
> +
> +&A53_0 {
> + cpu-supply = <&buck2_reg>;
> +};
> +
> +&A53_1 {
> + cpu-supply = <&buck2_reg>;
> +};
> +
> +&A53_2 {
> + cpu-supply = <&buck2_reg>;
> +};
> +
> +&A53_3 {
> + cpu-supply = <&buck2_reg>;
> +};
> +
> +&ddrc {
> + operating-points-v2 = <&ddrc_opp_table>;
> +
> + ddrc_opp_table: opp-table {
> + compatible = "operating-points-v2";
> +
> + opp-25M {
> + opp-hz = /bits/ 64 <25000000>;
> + };
> +
> + opp-100M {
> + opp-hz = /bits/ 64 <100000000>;
> + };
> +
> + opp-750M {
> + opp-hz = /bits/ 64 <750000000>;
> + };
> + };
> +};
> +
> +&ecspi1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_ecspi1>;
> + cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
> + status = "okay";
> +
> + flash at 0 { /* W25Q128FVSI */
> + compatible = "jedec,spi-nor";
> + m25p,fast-read;
> + spi-max-frequency = <50000000>;
> + reg = <0>;
> + };
> +};
> +
> +&ecspi2 { /* Feature connector SPI */
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_ecspi2>;
> + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
> + /* Disabled by default, unless feature board plugged in. */
> + status = "disabled";
> +};
> +
> +&ecspi3 { /* Display connector SPI */
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_ecspi3>;
> + cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>;
> + /* Disabled by default, unless display board plugged in. */
> + status = "disabled";
> +};
> +
> +&fec1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_fec1>;
> + phy-mode = "rgmii-id";
> + phy-handle = <&fec1_phy>;
> + phy-supply = <&buck4_reg>;
> + fsl,magic-packet;
> + status = "okay";
> +
> + mdio {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + /* Atheros AR8031 PHY */
> + fec1_phy: ethernet-phy at 0 {
> + compatible = "ethernet-phy-ieee802.3-c22";
> + reg = <0>;
> + /*
> + * Dedicated ENET_WOL# signal is unused, the PHY
> + * can wake the SoC up via INT signal as well.
> + */
> + interrupts-extended = <&gpio1 15 IRQ_TYPE_LEVEL_LOW>;
> + reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
> + reset-assert-us = <10000>;
> + reset-deassert-us = <10000>;
> + qca,clk-out-frequency = <125000000>;
> + qca,clk-out-strength = <AR803X_STRENGTH_FULL>;
> + qca,keep-pll-enabled;
> + vddio-supply = <&vddio>;
> +
> + vddio: vddio-regulator {
> + regulator-name = "VDDIO";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + };
> +
> + vddh: vddh-regulator {
> + regulator-name = "VDDH";
> + };
> + };
> + };
> +};
> +
> +&gpio1 {
> + gpio-line-names =
> + "", "ENET_RST#", "WDOG_B#", "PMIC_INT#",
> + "", "M2-B_PCIE_RST#", "M2-B_PCIE_WAKE#", "RTC_IRQ#",
> + "WDOG_KICK#", "M2-B_PCIE_CLKREQ#",
> + "USB1_OTG_ID_3V3", "ENET_WOL#",
> + "", "", "", "ENET_INT#",
> + "", "", "", "", "", "", "", "",
> + "", "", "", "", "", "", "", "";
> +};
> +
> +&gpio2 {
> + gpio-line-names =
> + "MEMCFG2", "MEMCFG1", "DSI_RESET_1V8#", "DSI_IRQ_1V8#",
> + "M2-B_FULL_CARD_PWROFF_1V8#", "EEPROM_WP_1V8#",
> + "PCIE_CLK_GEN_CLKPWRGD_PD_1V8#", "GRAPHICS_PRSNT_1V8#",
> + "MEMCFG0", "WDOG_EN",
> + "M2-B_W_DISABLE1_WWAN_1V8#", "M2-B_W_DISABLE2_GPS_1V8#",
> + "", "", "", "",
> + "", "", "", "SD2_RESET#", "", "", "", "",
> + "", "", "", "", "", "", "", "";
> +};
> +
> +&gpio3 {
> + gpio-line-names =
> + "BL_ENABLE_1V8", "PG_V_IN_VAR#", "", "",
> + "", "", "TFT_ENABLE_1V8", "GRAPHICS_GPIO0_1V8",
> + "CSI_PD_1V8", "CSI_RESET_1V8#", "", "",
> + "", "", "", "",
> + "", "", "", "M2-B_WAKE_WWAN_1V8#",
> + "M2-B_RESET_1V8#", "", "", "",
> + "", "", "", "", "", "", "", "";
> +};
> +
> +&gpio4 {
> + gpio-line-names =
> + "NC0", "NC1", "BOOTCFG0", "BOOTCFG1",
> + "BOOTCFG2", "BOOTCFG3", "BOOTCFG4", "BOOTCFG5",
> + "BOOTCFG6", "BOOTCFG7", "NC10", "NC11",
> + "BOOTCFG8", "BOOTCFG9", "BOOTCFG10", "BOOTCFG11",
> + "BOOTCFG12", "BOOTCFG13", "BOOTCFG14", "BOOTCFG15",
> + "NC20", "", "", "",
> + "", "CAN_INT#", "CAN_RST#", "GPIO4_IO27",
> + "DIS_USB_DN2", "", "", "";
> +};
> +
> +&gpio5 {
> + gpio-line-names =
> + "", "DIS_USB_DN1", "USBHUB_RESET#", "GPIO5_IO03",
> + "GPIO5_IO04", "", "", "",
> + "", "SPI1_CS#", "", "",
> + "", "SPI2_CS#", "I2C1_SCL_3V3", "I2C1_SDA_3V3",
> + "I2C2_SCL_3V3", "I2C2_SDA_3V3", "I2C3_SCL_3V3", "I2C3_SDA_3V3",
> + "I2C4_SCL_3V3", "I2C4_SDA_3V3", "", "",
> + "", "SPI3_CS#", "", "", "", "", "", "";
> +};
> +
> +&i2c1 {
> + /* IMX8MM ERRATA e7805 -- I2C is limited to 384 kHz due to SoC bug */
> + clock-frequency = <100000>;
> + pinctrl-names = "default", "gpio";
> + pinctrl-0 = <&pinctrl_i2c1>;
> + pinctrl-1 = <&pinctrl_i2c1_gpio>;
> + scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
> + sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
> + status = "okay";
> +
> + pmic: pmic at 4b {
> + compatible = "rohm,bd71847";
> + reg = <0x4b>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_pmic>;
> + interrupt-parent = <&gpio1>;
> + interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
> + rohm,reset-snvs-powered;
> +
> + /*
> + * i.MX 8M Mini Data Sheet for Consumer Products
> + * 3.1.3 Operating ranges
> + * MIMX8MM4DVTLZAA
> + */
> + regulators {
> + /* VDD_SOC */
> + buck1_reg: BUCK1 {
> + regulator-name = "buck1";
> + regulator-min-microvolt = <850000>;
> + regulator-max-microvolt = <850000>;
> + regulator-boot-on;
> + regulator-always-on;
> + regulator-ramp-delay = <1250>;
> + };
> +
> + /* VDD_ARM */
> + buck2_reg: BUCK2 {
> + regulator-name = "buck2";
> + regulator-min-microvolt = <850000>;
> + regulator-max-microvolt = <1050000>;
> + regulator-boot-on;
> + regulator-always-on;
> + regulator-ramp-delay = <1250>;
> + rohm,dvs-run-voltage = <1000000>;
> + rohm,dvs-idle-voltage = <950000>;
> + };
> +
> + /* VDD_DRAM, BUCK5 */
> + buck3_reg: BUCK3 {
> + regulator-name = "buck3";
> + /* 1.5 GHz DDR bus clock */
> + regulator-min-microvolt = <900000>;
> + regulator-max-microvolt = <1000000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + /* 3V3_VDD, BUCK6 */
> + buck4_reg: BUCK4 {
> + regulator-name = "buck4";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + /* 1V8_VDD, BUCK7 */
> + buck5_reg: BUCK5 {
> + regulator-name = "buck5";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + /* 1V1_NVCC_DRAM, BUCK8 */
> + buck6_reg: BUCK6 {
> + regulator-name = "buck6";
> + regulator-min-microvolt = <1100000>;
> + regulator-max-microvolt = <1100000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + /* 1V8_NVCC_SNVS */
> + ldo1_reg: LDO1 {
> + regulator-name = "ldo1";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + /* 0V8_VDD_SNVS */
> + ldo2_reg: LDO2 {
> + regulator-name = "ldo2";
> + regulator-min-microvolt = <800000>;
> + regulator-max-microvolt = <800000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + /* 1V8_VDDA */
> + ldo3_reg: LDO3 {
> + regulator-name = "ldo3";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + /* 0V9_VDD_PHY */
> + ldo4_reg: LDO4 {
> + regulator-name = "ldo4";
> + regulator-min-microvolt = <900000>;
> + regulator-max-microvolt = <900000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + /* 1V2_VDD_PHY */
> + ldo6_reg: LDO6 {
> + regulator-name = "ldo6";
> + regulator-min-microvolt = <1200000>;
> + regulator-max-microvolt = <1200000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> + };
> + };
> +};
> +
> +&i2c2 {
> + /* IMX8MM ERRATA e7805 -- I2C is limited to 384 kHz due to SoC bug */
> + clock-frequency = <320000>;
> + pinctrl-names = "default", "gpio";
> + pinctrl-0 = <&pinctrl_i2c2>;
> + pinctrl-1 = <&pinctrl_i2c2_gpio>;
> + scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
> + sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
> + status = "okay";
> +
> + usb-hub at 2c {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_usb_hub>;
> + compatible = "microchip,usb2514bi";
> + reg = <0x2c>;
> + individual-port-switching;
> + reset-gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
> + self-powered;
> + };
> +
> + eeprom: eeprom at 50 {
> + compatible = "atmel,24c32";
> + reg = <0x50>;
> + pagesize = <32>;
> + };
> +
> + rtc: rtc at 68 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_rtc>;
> + compatible = "st,m41t62";
> + reg = <0x68>;
> + interrupts-extended = <&gpio1 7 IRQ_TYPE_LEVEL_LOW>;
> + };
> +
> + pcieclk: clk at 6a {
> + compatible = "renesas,9fgv0241";
> + reg = <0x6a>;
> + clocks = <&clk_xtal25>;
> + #clock-cells = <1>;
> + };
> +};
> +
> +&i2c3 { /* Display connector I2C */
> + /* IMX8MM ERRATA e7805 -- I2C is limited to 384 kHz due to SoC bug */
> + clock-frequency = <320000>;
> + pinctrl-names = "default", "gpio";
> + pinctrl-0 = <&pinctrl_i2c3>;
> + pinctrl-1 = <&pinctrl_i2c3_gpio>;
> + scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
> + sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
> + status = "okay";
> +};
> +
> +&i2c4 { /* Feature connector I2C */
> + /* IMX8MM ERRATA e7805 -- I2C is limited to 384 kHz due to SoC bug */
> + clock-frequency = <320000>;
> + pinctrl-names = "default", "gpio";
> + pinctrl-0 = <&pinctrl_i2c4>;
> + pinctrl-1 = <&pinctrl_i2c4_gpio>;
> + scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
> + sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
> + status = "okay";
> +};
> +
> +&iomuxc {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_hog_feature>, <&pinctrl_hog_misc>,
> + <&pinctrl_hog_panel>, <&pinctrl_hog_sbc>,
> + <&pinctrl_panel_expansion>;
> +
> + pinctrl_ecspi1: ecspi1-grp {
> + fsl,pins = <
> + MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x44
> + MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x44
> + MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x44
> + MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x40
> + >;
> + };
> +
> + pinctrl_ecspi2: ecspi2-grp {
> + fsl,pins = <
> + MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x44
> + MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x44
> + MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x44
> + MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x40
> + >;
> + };
> +
> + pinctrl_ecspi3: ecspi3-grp {
> + fsl,pins = <
> + MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x44
> + MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x44
> + MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO 0x44
> + MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x40
> + >;
> + };
> +
> + pinctrl_fec1: fec1-grp {
> + fsl,pins = <
> + MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
> + MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
> + MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
> + MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
> + MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
> + MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
> + MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
> + MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
> + MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
> + MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
> + MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
> + MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
> + MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
> + MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
> + /* ENET_RST# */
> + MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x6
> + /* ENET_WOL# */
> + MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x40000090
> + /* ENET_INT# */
> + MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x40000090
> + >;
> + };
> +
> + pinctrl_hog_feature: hog-feature-grp {
> + fsl,pins = <
> + /* GPIO4_IO27 */
> + MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x40000006
> + /* GPIO5_IO03 */
> + MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000006
> + /* GPIO5_IO04 */
> + MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x40000006
> +
> + /* CAN_INT# */
> + MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25 0x40000090
> + /* CAN_RST# */
> + MX8MM_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x26
> + >;
> + };
> +
> + pinctrl_hog_panel: hog-panel-grp {
> + fsl,pins = <
> + /* GRAPHICS_GPIO0_1V8 */
> + MX8MM_IOMUXC_NAND_DATA01_GPIO3_IO7 0x26
> + >;
> + };
> +
> + pinctrl_hog_misc: hog-misc-grp {
> + fsl,pins = <
> + /* PG_V_IN_VAR# */
> + MX8MM_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x40000000
> + /* CSI_PD_1V8 */
> + MX8MM_IOMUXC_NAND_DATA02_GPIO3_IO8 0x0
> + /* CSI_RESET_1V8# */
> + MX8MM_IOMUXC_NAND_DATA03_GPIO3_IO9 0x0
> +
> + /* DIS_USB_DN1 */
> + MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1 0x0
> + /* DIS_USB_DN2 */
> + MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x0
> +
> + /* EEPROM_WP_1V8# */
> + MX8MM_IOMUXC_SD1_DATA3_GPIO2_IO5 0x100
> + /* PCIE_CLK_GEN_CLKPWRGD_PD_1V8# */
> + MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x0
> + /* GRAPHICS_PRSNT_1V8# */
> + MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7 0x40000000
> +
> + /* CLK_CCM_CLKO1_3V3 */
> + MX8MM_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x10
> + >;
> + };
> +
> + pinctrl_hog_sbc: hog-sbc-grp {
> + fsl,pins = <
> + /* MEMCFG[0..2] straps */
> + MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x40000140
> + MX8MM_IOMUXC_SD1_CMD_GPIO2_IO1 0x40000140
> + MX8MM_IOMUXC_SD1_CLK_GPIO2_IO0 0x40000140
> +
> + /* BOOT_CFG[0..15] straps */
> + MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x40000000
> + MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x40000000
> + MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x40000000
> + MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x40000000
> + MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x40000000
> + MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x40000000
> + MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x40000000
> + MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x40000000
> + MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x40000000
> + MX8MM_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x40000000
> + MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x40000000
> + MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x40000000
> + MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x40000000
> + MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x40000000
> + MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x40000000
> + MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x40000000
> +
> + /* Not connected pins */
> + MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x0
> + MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x0
> + MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11 0x0
> + MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x0
> + MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x0
> + >;
> + };
> +
> + pinctrl_i2c1: i2c1-grp {
> + fsl,pins = <
> + MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x40000084
> + MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x40000084
> + >;
> + };
> +
> + pinctrl_i2c1_gpio: i2c1-gpio-grp {
> + fsl,pins = <
> + MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x84
> + MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x84
> + >;
> + };
> +
> + pinctrl_i2c2: i2c2-grp {
> + fsl,pins = <
> + MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x40000084
> + MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x40000084
> + >;
> + };
> +
> + pinctrl_i2c2_gpio: i2c2-gpio-grp {
> + fsl,pins = <
> + MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x84
> + MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x84
> + >;
> + };
> +
> + pinctrl_i2c3: i2c3-grp {
> + fsl,pins = <
> + MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x40000084
> + MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x40000084
> + >;
> + };
> +
> + pinctrl_i2c3_gpio: i2c3-gpio-grp {
> + fsl,pins = <
> + MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x84
> + MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x84
> + >;
> + };
> +
> + pinctrl_i2c4: i2c4-grp {
> + fsl,pins = <
> + MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x40000084
> + MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x40000084
> + >;
> + };
> +
> + pinctrl_i2c4_gpio: i2c4-gpio-grp {
> + fsl,pins = <
> + MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x84
> + MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x84
> + >;
> + };
> +
> + pinctrl_panel_backlight: panel-backlight-grp {
> + fsl,pins = <
> + /* BL_ENABLE_1V8 */
> + MX8MM_IOMUXC_NAND_ALE_GPIO3_IO0 0x104
> + >;
> + };
> +
> + pinctrl_panel_expansion: panel-expansion-grp {
> + fsl,pins = <
> + /* DSI_RESET_1V8# */
> + MX8MM_IOMUXC_SD1_DATA0_GPIO2_IO2 0x2
> + /* DSI_IRQ_1V8# */
> + MX8MM_IOMUXC_SD1_DATA1_GPIO2_IO3 0x40000090
> + >;
> + };
> +
> + pinctrl_panel_vcc_reg: panel-vcc-grp {
> + fsl,pins = <
> + /* TFT_ENABLE_1V8 */
> + MX8MM_IOMUXC_NAND_DATA00_GPIO3_IO6 0x104
> + >;
> + };
> +
> + pinctrl_panel_pwm: panel-pwm-grp {
> + fsl,pins = <
> + /* BL_PWM_3V3 */
> + MX8MM_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x12
> + >;
> + };
> +
> + pinctrl_pcie0: pcie-grp {
> + fsl,pins = <
> + /* M2-B_RESET_1V8# */
> + MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x102
> + /* M2-B_PCIE_RST# */
> + MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x2
> + /* M2-B_FULL_CARD_PWROFF_1V8# */
> + MX8MM_IOMUXC_SD1_DATA2_GPIO2_IO4 0x102
> + /* M2-B_W_DISABLE1_WWAN_1V8# */
> + MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x102
> + /* M2-B_W_DISABLE2_GPS_1V8# */
> + MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11 0x102
> + /* CLK_M2_32K768 */
> + MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x14
> + /* M2-B_WAKE_WWAN_1V8# */
> + MX8MM_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x40000140
> + /* M2-B_PCIE_WAKE# */
> + MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x40000140
> + /* M2-B_PCIE_CLKREQ# */
> + MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x40000140
> + >;
> + };
> +
> + pinctrl_pmic: pmic-grp {
> + fsl,pins = <
> + MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x40000090
> + >;
> + };
> +
> + pinctrl_rtc: rtc-grp {
> + fsl,pins = <
> + /* RTC_IRQ# */
> + MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x40000090
> + >;
> + };
> +
> + pinctrl_sai5: sai5-grp {
> + fsl,pins = <
> + MX8MM_IOMUXC_SAI5_MCLK_SAI5_MCLK 0x100
> + MX8MM_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x0
> + MX8MM_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x100
> + MX8MM_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x100
> + MX8MM_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x100
> + >;
> + };
> +
> + pinctrl_uart1: uart1-grp {
> + fsl,pins = <
> + MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x90
> + MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x90
> + MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x50
> + MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x50
> + >;
> + };
> +
> + pinctrl_uart2: uart2-grp {
> + fsl,pins = <
> + MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x50
> + MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x90
> + MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x50
> + MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x90
> + >;
> + };
> +
> + pinctrl_uart3: uart3-grp {
> + fsl,pins = <
> + MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x40
> + MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x40
> + >;
> + };
> +
> + pinctrl_uart4: uart4-grp {
> + fsl,pins = <
> + MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x40
> + MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x40
> + >;
> + };
> +
> + pinctrl_usb_hub: usb-hub-grp {
> + fsl,pins = <
> + /* USBHUB_RESET# */
> + MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x4
> + >;
> + };
> +
> + pinctrl_usb_otg1: usb-otg1-grp {
> + fsl,pins = <
> + MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x40000000
> + MX8MM_IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x4
> + MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x40000090
> + >;
> + };
> +
> + pinctrl_usdhc2_vcc_reg: usdhc2-vcc-reg-grp {
> + fsl,pins = <
> + MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x4
> + >;
> + };
> +
> + pinctrl_usdhc2: usdhc2-grp {
> + fsl,pins = <
> + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
> + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
> + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
> + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
> + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
> + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
> + MX8MM_IOMUXC_SD2_WP_USDHC2_WP 0x400000d6
> + MX8MM_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x0d6
> + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
> + >;
> + };
> +
> + pinctrl_usdhc2_100mhz: usdhc2-100mhz-grp {
> + fsl,pins = <
> + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
> + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
> + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
> + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
> + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
> + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
> + MX8MM_IOMUXC_SD2_WP_USDHC2_WP 0x400000d6
> + MX8MM_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x0d6
> + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
> + >;
> + };
> +
> + pinctrl_usdhc2_200mhz: usdhc2-200mhz-grp {
> + fsl,pins = <
> + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
> + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
> + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
> + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
> + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
> + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
> + MX8MM_IOMUXC_SD2_WP_USDHC2_WP 0x400000d6
> + MX8MM_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x0d6
> + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
> + >;
> + };
> +
> + pinctrl_usdhc3: usdhc3-grp {
> + fsl,pins = <
> + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
> + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
> + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
> + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
> + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
> + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
> + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
> + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
> + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
> + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
> + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
> + MX8MM_IOMUXC_NAND_READY_B_SD3_RESET_B 0x40
> + >;
> + };
> +
> + pinctrl_usdhc3_100mhz: usdhc3-100mhz-grp {
> + fsl,pins = <
> + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
> + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
> + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
> + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
> + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
> + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
> + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
> + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
> + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
> + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
> + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
> + MX8MM_IOMUXC_NAND_READY_B_SD3_RESET_B 0x40
> + >;
> + };
> +
> + pinctrl_usdhc3_200mhz: usdhc3-200mhz-grp {
> + fsl,pins = <
> + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
> + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
> + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
> + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
> + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
> + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
> + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
> + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
> + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
> + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
> + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
> + MX8MM_IOMUXC_NAND_READY_B_SD3_RESET_B 0x40
> + >;
> + };
> +
> + pinctrl_watchdog_gpio: watchdog-gpio-grp {
> + fsl,pins = <
> + /* WDOG_B# */
> + MX8MM_IOMUXC_GPIO1_IO02_GPIO1_IO2 0x26
> + /* WDOG_EN -- ungate WDT RESET# signal propagation */
> + MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x6
> + /* WDOG_KICK# / WDI */
> + MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x26
> + >;
> + };
> +};
> +
> +&pcie_phy {
> + fsl,clkreq-unsupported; /* CLKREQ_B is not connected to suitable input */
> + fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
> + fsl,tx-deemph-gen1 = <0x2d>;
> + fsl,tx-deemph-gen2 = <0xf>;
> + clocks = <&pcieclk 0>;
> + status = "okay";
> +};
> +
> +&pcie0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_pcie0>;
> + reset-gpio = <&gpio1 5 GPIO_ACTIVE_LOW>;
> + clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
> + <&pcieclk 0>;
> + clock-names = "pcie", "pcie_aux", "pcie_bus";
> + assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
> + <&clk IMX8MM_CLK_PCIE1_CTRL>;
> + assigned-clock-rates = <10000000>, <250000000>;
> + assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
> + <&clk IMX8MM_SYS_PLL2_250M>;
> + status = "okay";
> +};
> +
> +&pwm1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_panel_pwm>;
> + /* Disabled by default, unless display board plugged in. */
> + status = "disabled";
> +};
> +
> +&sai5 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_sai5>;
> + fsl,sai-mclk-direction-output;
> + /* Input into codec PLL */
> + assigned-clocks = <&clk IMX8MM_CLK_SAI5>;
> + assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL2_OUT>;
> + assigned-clock-rates = <22579200>;
> + /* Disabled by default, unless display board plugged in. */
> + status = "disabled";
> +};
> +
> +&uart1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart1>;
> + uart-has-rtscts;
> + status = "disabled";
> +};
> +
> +&uart2 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart2>;
> + status = "disabled";
> +};
> +
> +&uart3 { /* A53 Debug */
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart3>;
> + status = "okay";
> +};
> +
> +&uart4 { /* M4 Debug */
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart4>;
> + /* UART4 is reserved for CM and RDC blocks CA access to UART4. */
> + status = "disabled";
> +};
> +
> +&usbotg1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_usb_otg1>;
> + dr_mode = "otg";
> + status = "okay";
> +};
> +
> +&usbotg2 {
> + dr_mode = "host";
> + status = "okay";
> +};
> +
> +&usdhc2 { /* MicroSD */
> + assigned-clocks = <&clk IMX8MM_CLK_USDHC2_ROOT>;
> + pinctrl-names = "default", "state_100mhz", "state_200mhz";
> + pinctrl-0 = <&pinctrl_usdhc2>;
> + pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
> + pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
> + bus-width = <4>;
> + vmmc-supply = <®_usdhc2_vcc>;
> + status = "okay";
> +};
> +
> +&usdhc3 { /* eMMC */
> + assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>;
> + assigned-clock-rates = <400000000>;
> + pinctrl-names = "default", "state_100mhz", "state_200mhz";
> + pinctrl-0 = <&pinctrl_usdhc3>;
> + pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
> + pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
> + bus-width = <8>;
> + non-removable;
> + vmmc-supply = <&buck4_reg>;
> + vqmmc-supply = <&buck5_reg>;
> + status = "okay";
> +};
> +
> +&wdog1 {
> + status = "okay";
> +};
> diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig
> index fae70499953..7f09d7b26a8 100644
> --- a/arch/arm/mach-imx/imx8m/Kconfig
> +++ b/arch/arm/mach-imx/imx8m/Kconfig
> @@ -46,6 +46,13 @@ config TARGET_IMX8MQ_PHANBELL
> select IMX8MQ
> select IMX8M_LPDDR4
>
> +config TARGET_IMX8MM_DATA_MODUL_EDM_SBC
> + bool "Data Modul eDM SBC i.MX8M Mini"
> + select BINMAN
> + select IMX8MM
> + select IMX8M_LPDDR4
> + select SUPPORT_SPL
> +
> config TARGET_IMX8MM_EVK
> bool "imx8mm LPDDR4 EVK board"
> select BINMAN
> @@ -209,6 +216,7 @@ source "board/advantech/imx8mp_rsb3720a1/Kconfig"
> source "board/beacon/imx8mm/Kconfig"
> source "board/beacon/imx8mn/Kconfig"
> source "board/compulab/imx8mm-cl-iot-gate/Kconfig"
> +source "board/data_modul/imx8mm_edm_sbc/Kconfig"
> source "board/engicam/imx8mm/Kconfig"
> source "board/freescale/imx8mq_evk/Kconfig"
> source "board/freescale/imx8mm_evk/Kconfig"
> diff --git a/board/data_modul/imx8mm_edm_sbc/Kconfig b/board/data_modul/imx8mm_edm_sbc/Kconfig
> new file mode 100644
> index 00000000000..df9871c2240
> --- /dev/null
> +++ b/board/data_modul/imx8mm_edm_sbc/Kconfig
> @@ -0,0 +1,12 @@
> +if TARGET_IMX8MM_DATA_MODUL_EDM_SBC
> +
> +config SYS_BOARD
> + default "imx8mm_edm_sbc"
> +
> +config SYS_VENDOR
> + default "data_modul"
> +
> +config SYS_CONFIG_NAME
> + default "imx8mm_data_modul_edm_sbc"
> +
> +endif
> diff --git a/board/data_modul/imx8mm_edm_sbc/MAINTAINERS b/board/data_modul/imx8mm_edm_sbc/MAINTAINERS
> new file mode 100644
> index 00000000000..72659c081e2
> --- /dev/null
> +++ b/board/data_modul/imx8mm_edm_sbc/MAINTAINERS
> @@ -0,0 +1,8 @@
> +Data Modul eDM SBC i.MX8M Mini
> +M: Marek Vasut <marex at denx.de>
> +S: Maintained
> +F: arch/arm/dts/imx8mm-data-modul-edm-sbc.dts
> +F: arch/arm/dts/imx8mm-data-modul-edm-sbc-u-boot.dtsi
> +F: board/data_modul/imx8mm_data_modul_edm_sbc/
> +F: configs/imx8mm_data_modul_edm_sbc_defconfig
> +F: include/configs/imx8mm_data_modul_edm_sbc.h
> diff --git a/board/data_modul/imx8mm_edm_sbc/Makefile b/board/data_modul/imx8mm_edm_sbc/Makefile
> new file mode 100644
> index 00000000000..eaba85d65b8
> --- /dev/null
> +++ b/board/data_modul/imx8mm_edm_sbc/Makefile
> @@ -0,0 +1,13 @@
> +#
> +# Copyright (C) 2022 Marek Vasut <marex at denx.de>
> +#
> +# SPDX-License-Identifier: GPL-2.0+
> +#
> +
> +ifdef CONFIG_SPL_BUILD
> +obj-y += spl.o lpddr4_timing_2G_32.o lpddr4_timing_4G_32.o
> +else
> +obj-y += imx8mm_data_modul_edm_sbc.o
> +endif
> +
> +obj-y += common.o
> diff --git a/board/data_modul/imx8mm_edm_sbc/common.c b/board/data_modul/imx8mm_edm_sbc/common.c
> new file mode 100644
> index 00000000000..713f789da67
> --- /dev/null
> +++ b/board/data_modul/imx8mm_edm_sbc/common.c
> @@ -0,0 +1,37 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2022 Marek Vasut <marex at denx.de>
> + */
> +
> +#include <common.h>
> +#include <asm/io.h>
> +#include <asm-generic/gpio.h>
> +
> +#include "lpddr4_timing.h"
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +u8 dmo_get_memcfg(void)
> +{
> + struct gpio_desc gpio[4];
> + u8 memcfg = 0;
> + ofnode node;
> + int i, ret;
> +
> + node = ofnode_path("/config");
> + if (!ofnode_valid(node)) {
> + printf("%s: no /config node?\n", __func__);
> + return BIT(2) | BIT(0);
> + }
> +
> + ret = gpio_request_list_by_name_nodev(node,
> + "dmo,ram-coding-gpios",
> + gpio, ARRAY_SIZE(gpio),
> + GPIOD_IS_IN);
> + for (i = 0; i < ret; i++)
> + memcfg |= !!dm_gpio_get_value(&(gpio[i])) << i;
> +
> + gpio_free_list_nodev(gpio, ret);
> +
> + return memcfg;
> +}
> diff --git a/board/data_modul/imx8mm_edm_sbc/imx8mm_data_modul_edm_sbc.c b/board/data_modul/imx8mm_edm_sbc/imx8mm_data_modul_edm_sbc.c
> new file mode 100644
> index 00000000000..46cb6f77b59
> --- /dev/null
> +++ b/board/data_modul/imx8mm_edm_sbc/imx8mm_data_modul_edm_sbc.c
> @@ -0,0 +1,110 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2022 Marek Vasut <marex at denx.de>
> + */
> +
> +#include <common.h>
> +#include <asm/arch/clock.h>
> +#include <asm/arch/sys_proto.h>
> +#include <asm/io.h>
> +#include <asm/mach-imx/boot_mode.h>
> +#include <dm.h>
> +#include <i2c_eeprom.h>
> +#include <malloc.h>
> +#include <net.h>
> +#include <spl.h>
> +
> +#include "lpddr4_timing.h"
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +int mach_cpu_init(void)
> +{
> + icache_enable();
> + return 0;
> +}
> +
> +int board_phys_sdram_size(phys_size_t *size)
> +{
> + u8 memcfg = dmo_get_memcfg();
> +
> + *size = (4ULL >> ((memcfg >> 1) & 0x3)) * SZ_1G;
> +
> + return 0;
> +}
> +
> +/* IMX8M SNVS registers needed for the bootcount functionality */
> +#define SNVS_BASE_ADDR 0x30370000
> +#define SNVS_LPSR 0x4c
> +#define SNVS_LPLVDR 0x64
> +#define SNVS_LPPGDR_INIT 0x41736166
> +
> +static void setup_snvs(void)
> +{
> + /* Enable SNVS clock */
> + clock_enable(CCGR_SNVS, 1);
> + /* Initialize glitch detect */
> + writel(SNVS_LPPGDR_INIT, SNVS_BASE_ADDR + SNVS_LPLVDR);
> + /* Clear interrupt status */
> + writel(0xffffffff, SNVS_BASE_ADDR + SNVS_LPSR);
> +}
> +
> +static void setup_mac_address(void)
> +{
> + unsigned char enetaddr[6];
> + struct udevice *dev;
> + int off, ret;
> +
> + ret = eth_env_get_enetaddr("ethaddr", enetaddr);
> + if (ret) /* ethaddr is already set */
> + return;
> +
> + off = fdt_path_offset(gd->fdt_blob, "eeprom0");
> + if (off < 0) {
> + printf("%s: No eeprom0 path offset\n", __func__);
> + return;
> + }
> +
> + ret = uclass_get_device_by_of_offset(UCLASS_I2C_EEPROM, off, &dev);
> + if (ret) {
> + printf("Cannot find EEPROM!\n");
> + return;
> + }
> +
> + ret = i2c_eeprom_read(dev, 0xb0, enetaddr, 0x6);
> + if (ret) {
> + printf("Error reading configuration EEPROM!\n");
> + return;
> + }
> +
> + if (is_valid_ethaddr(enetaddr))
> + eth_env_set_enetaddr("ethaddr", enetaddr);
> +}
> +
> +static void setup_boot_device(void)
> +{
> + int boot_device = get_boot_device();
> + char *devnum;
> +
> + devnum = env_get("devnum");
> + if (devnum) /* devnum is already set */
> + return;
> +
> + if (boot_device == MMC3_BOOT) /* eMMC */
> + env_set_ulong("devnum", 0);
> + else
> + env_set_ulong("devnum", 1);
> +}
> +
> +int board_init(void)
> +{
> + setup_snvs();
> + return 0;
> +}
> +
> +int board_late_init(void)
> +{
> + setup_boot_device();
> + setup_mac_address();
> + return 0;
> +}
> diff --git a/board/data_modul/imx8mm_edm_sbc/imximage.cfg b/board/data_modul/imx8mm_edm_sbc/imximage.cfg
> new file mode 100644
> index 00000000000..fa0b618128a
> --- /dev/null
> +++ b/board/data_modul/imx8mm_edm_sbc/imximage.cfg
> @@ -0,0 +1,8 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright 2019 NXP
> + */
> +
> +FIT
> +BOOT_FROM sd
> +LOADER u-boot-spl-ddr.bin 0x7E1000
> diff --git a/board/data_modul/imx8mm_edm_sbc/lpddr4_timing.h b/board/data_modul/imx8mm_edm_sbc/lpddr4_timing.h
> new file mode 100644
> index 00000000000..1fab9b14051
> --- /dev/null
> +++ b/board/data_modul/imx8mm_edm_sbc/lpddr4_timing.h
> @@ -0,0 +1,14 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright 2022 Marek Vasut <marex at denx.de>
> + */
> +
> +#ifndef __LPDDR4_TIMING_H__
> +#define __LPDDR4_TIMING_H__
> +
> +extern struct dram_timing_info dmo_imx8mm_sbc_dram_timing_16_32;
> +extern struct dram_timing_info dmo_imx8mm_sbc_dram_timing_32_32;
> +
> +u8 dmo_get_memcfg(void);
> +
> +#endif /* __LPDDR4_TIMING_H__ */
> diff --git a/board/data_modul/imx8mm_edm_sbc/lpddr4_timing_2G_32.c b/board/data_modul/imx8mm_edm_sbc/lpddr4_timing_2G_32.c
> new file mode 100644
> index 00000000000..c2abcb54895
> --- /dev/null
> +++ b/board/data_modul/imx8mm_edm_sbc/lpddr4_timing_2G_32.c
> @@ -0,0 +1,1845 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2019 NXP
> + *
> + * Generated code from MX8M_DDR_tool
> + * Align with uboot version:
> + * imx_v2018.03_4.14.78_1.0.0_ga ~ imx_v2018.04_4.19.35_1.0.0_ga
> + */
> +
> +#include <linux/kernel.h>
> +#include <asm/arch/ddr.h>
> +
> +static struct dram_cfg_param ddr_ddrc_cfg[] = {
> + /** Initialize DDRC registers **/
> + { 0x3d400304, 0x1 },
> + { 0x3d400030, 0x1 },
> + { 0x3d400000, 0xa1080020 },
> + { 0x3d400020, 0x203 },
> + { 0x3d400024, 0x3a980 },
> + { 0x3d400064, 0x5b00d2 },
> + { 0x3d4000d0, 0xc00305ba },
> + { 0x3d4000d4, 0x940000 },
> + { 0x3d4000dc, 0xd4002d },
> + { 0x3d4000e0, 0x310000 },
> + { 0x3d4000e8, 0x66004d },
> + { 0x3d4000ec, 0x16004d },
> + { 0x3d400100, 0x191e1920 },
> + { 0x3d400104, 0x60630 },
> + { 0x3d40010c, 0xb0b000 },
> + { 0x3d400110, 0xe04080e },
> + { 0x3d400114, 0x2040c0c },
> + { 0x3d400118, 0x1010007 },
> + { 0x3d40011c, 0x401 },
> + { 0x3d400130, 0x20600 },
> + { 0x3d400134, 0xc100002 },
> + { 0x3d400138, 0xd8 },
> + { 0x3d400144, 0x96004b },
> + { 0x3d400180, 0x2ee0017 },
> + { 0x3d400184, 0x2605b8e },
> + { 0x3d400188, 0x0 },
> + { 0x3d400190, 0x497820a },
> + { 0x3d400194, 0x80303 },
> + { 0x3d4001b4, 0x170a },
> + { 0x3d4001a0, 0xe0400018 },
> + { 0x3d4001a4, 0xdf00e4 },
> + { 0x3d4001a8, 0x80000000 },
> + { 0x3d4001b0, 0x11 },
> + { 0x3d4001c0, 0x1 },
> + { 0x3d4001c4, 0x1 },
> + { 0x3d4000f4, 0xc99 },
> + { 0x3d400108, 0x70e1617 },
> + { 0x3d400200, 0x1f },
> + { 0x3d40020c, 0x0 },
> + { 0x3d400210, 0x1f1f },
> + { 0x3d400204, 0x80808 },
> + { 0x3d400214, 0x7070707 },
> + { 0x3d400218, 0x7070707 },
> + { 0x3d400250, 0x29001701 },
> + { 0x3d400254, 0x2c },
> + { 0x3d40025c, 0x4000030 },
> + { 0x3d400264, 0x900093e7 },
> + { 0x3d40026c, 0x2005574 },
> + { 0x3d400400, 0x111 },
> + { 0x3d400408, 0x72ff },
> + { 0x3d400494, 0x2100e07 },
> + { 0x3d400498, 0x620096 },
> + { 0x3d40049c, 0x1100e07 },
> + { 0x3d4004a0, 0xc8012c },
> + { 0x3d402020, 0x1 },
> + { 0x3d402024, 0x7d00 },
> + { 0x3d402050, 0x20d040 },
> + { 0x3d402064, 0xc001c },
> + { 0x3d4020dc, 0x840000 },
> + { 0x3d4020e0, 0x310000 },
> + { 0x3d4020e8, 0x66004d },
> + { 0x3d4020ec, 0x16004d },
> + { 0x3d402100, 0xa040305 },
> + { 0x3d402104, 0x30407 },
> + { 0x3d402108, 0x203060b },
> + { 0x3d40210c, 0x505000 },
> + { 0x3d402110, 0x2040202 },
> + { 0x3d402114, 0x2030202 },
> + { 0x3d402118, 0x1010004 },
> + { 0x3d40211c, 0x301 },
> + { 0x3d402130, 0x20300 },
> + { 0x3d402134, 0xa100002 },
> + { 0x3d402138, 0x1d },
> + { 0x3d402144, 0x14000a },
> + { 0x3d402180, 0x640004 },
> + { 0x3d402190, 0x3818200 },
> + { 0x3d402194, 0x80303 },
> + { 0x3d4021b4, 0x100 },
> + { 0x3d4020f4, 0xc99 },
> + { 0x3d403020, 0x1 },
> + { 0x3d403024, 0x1f40 },
> + { 0x3d403050, 0x20d040 },
> + { 0x3d403064, 0x30007 },
> + { 0x3d4030dc, 0x840000 },
> + { 0x3d4030e0, 0x310000 },
> + { 0x3d4030e8, 0x66004d },
> + { 0x3d4030ec, 0x16004d },
> + { 0x3d403100, 0xa010102 },
> + { 0x3d403104, 0x30404 },
> + { 0x3d403108, 0x203060b },
> + { 0x3d40310c, 0x505000 },
> + { 0x3d403110, 0x2040202 },
> + { 0x3d403114, 0x2030202 },
> + { 0x3d403118, 0x1010004 },
> + { 0x3d40311c, 0x301 },
> + { 0x3d403130, 0x20300 },
> + { 0x3d403134, 0xa100002 },
> + { 0x3d403138, 0x8 },
> + { 0x3d403144, 0x50003 },
> + { 0x3d403180, 0x190004 },
> + { 0x3d403190, 0x3818200 },
> + { 0x3d403194, 0x80303 },
> + { 0x3d4031b4, 0x100 },
> + { 0x3d4030f4, 0xc99 },
> + { 0x3d400028, 0x0 },
> +};
> +
> +/* PHY Initialize Configuration */
> +static struct dram_cfg_param ddr_ddrphy_cfg[] = {
> + { 0x100a0, 0x6 },
> + { 0x100a1, 0x7 },
> + { 0x100a2, 0x0 },
> + { 0x100a3, 0x1 },
> + { 0x100a4, 0x3 },
> + { 0x100a5, 0x2 },
> + { 0x100a6, 0x4 },
> + { 0x100a7, 0x5 },
> + { 0x110a0, 0x0 },
> + { 0x110a1, 0x1 },
> + { 0x110a2, 0x5 },
> + { 0x110a3, 0x3 },
> + { 0x110a4, 0x2 },
> + { 0x110a5, 0x4 },
> + { 0x110a6, 0x6 },
> + { 0x110a7, 0x7 },
> + { 0x120a0, 0x0 },
> + { 0x120a1, 0x1 },
> + { 0x120a2, 0x5 },
> + { 0x120a3, 0x3 },
> + { 0x120a4, 0x2 },
> + { 0x120a5, 0x4 },
> + { 0x120a6, 0x6 },
> + { 0x120a7, 0x7 },
> + { 0x130a0, 0x6 },
> + { 0x130a1, 0x7 },
> + { 0x130a2, 0x0 },
> + { 0x130a3, 0x1 },
> + { 0x130a4, 0x3 },
> + { 0x130a5, 0x2 },
> + { 0x130a6, 0x4 },
> + { 0x130a7, 0x5 },
> + { 0x1005f, 0x1ff },
> + { 0x1015f, 0x1ff },
> + { 0x1105f, 0x1ff },
> + { 0x1115f, 0x1ff },
> + { 0x1205f, 0x1ff },
> + { 0x1215f, 0x1ff },
> + { 0x1305f, 0x1ff },
> + { 0x1315f, 0x1ff },
> + { 0x11005f, 0x1ff },
> + { 0x11015f, 0x1ff },
> + { 0x11105f, 0x1ff },
> + { 0x11115f, 0x1ff },
> + { 0x11205f, 0x1ff },
> + { 0x11215f, 0x1ff },
> + { 0x11305f, 0x1ff },
> + { 0x11315f, 0x1ff },
> + { 0x21005f, 0x1ff },
> + { 0x21015f, 0x1ff },
> + { 0x21105f, 0x1ff },
> + { 0x21115f, 0x1ff },
> + { 0x21205f, 0x1ff },
> + { 0x21215f, 0x1ff },
> + { 0x21305f, 0x1ff },
> + { 0x21315f, 0x1ff },
> + { 0x55, 0x1ff },
> + { 0x1055, 0x1ff },
> + { 0x2055, 0x1ff },
> + { 0x3055, 0x1ff },
> + { 0x4055, 0x1ff },
> + { 0x5055, 0x1ff },
> + { 0x6055, 0x1ff },
> + { 0x7055, 0x1ff },
> + { 0x8055, 0x1ff },
> + { 0x9055, 0x1ff },
> + { 0x200c5, 0x19 },
> + { 0x1200c5, 0x7 },
> + { 0x2200c5, 0x7 },
> + { 0x2002e, 0x2 },
> + { 0x12002e, 0x2 },
> + { 0x22002e, 0x2 },
> + { 0x90204, 0x0 },
> + { 0x190204, 0x0 },
> + { 0x290204, 0x0 },
> + { 0x20024, 0x1ab },
> + { 0x2003a, 0x0 },
> + { 0x120024, 0x1ab },
> + { 0x2003a, 0x0 },
> + { 0x220024, 0x1ab },
> + { 0x2003a, 0x0 },
> + { 0x20056, 0x3 },
> + { 0x120056, 0x3 },
> + { 0x220056, 0x3 },
> + { 0x1004d, 0xe00 },
> + { 0x1014d, 0xe00 },
> + { 0x1104d, 0xe00 },
> + { 0x1114d, 0xe00 },
> + { 0x1204d, 0xe00 },
> + { 0x1214d, 0xe00 },
> + { 0x1304d, 0xe00 },
> + { 0x1314d, 0xe00 },
> + { 0x11004d, 0xe00 },
> + { 0x11014d, 0xe00 },
> + { 0x11104d, 0xe00 },
> + { 0x11114d, 0xe00 },
> + { 0x11204d, 0xe00 },
> + { 0x11214d, 0xe00 },
> + { 0x11304d, 0xe00 },
> + { 0x11314d, 0xe00 },
> + { 0x21004d, 0xe00 },
> + { 0x21014d, 0xe00 },
> + { 0x21104d, 0xe00 },
> + { 0x21114d, 0xe00 },
> + { 0x21204d, 0xe00 },
> + { 0x21214d, 0xe00 },
> + { 0x21304d, 0xe00 },
> + { 0x21314d, 0xe00 },
> + { 0x10049, 0xeba },
> + { 0x10149, 0xeba },
> + { 0x11049, 0xeba },
> + { 0x11149, 0xeba },
> + { 0x12049, 0xeba },
> + { 0x12149, 0xeba },
> + { 0x13049, 0xeba },
> + { 0x13149, 0xeba },
> + { 0x110049, 0xeba },
> + { 0x110149, 0xeba },
> + { 0x111049, 0xeba },
> + { 0x111149, 0xeba },
> + { 0x112049, 0xeba },
> + { 0x112149, 0xeba },
> + { 0x113049, 0xeba },
> + { 0x113149, 0xeba },
> + { 0x210049, 0xeba },
> + { 0x210149, 0xeba },
> + { 0x211049, 0xeba },
> + { 0x211149, 0xeba },
> + { 0x212049, 0xeba },
> + { 0x212149, 0xeba },
> + { 0x213049, 0xeba },
> + { 0x213149, 0xeba },
> + { 0x43, 0x63 },
> + { 0x1043, 0x63 },
> + { 0x2043, 0x63 },
> + { 0x3043, 0x63 },
> + { 0x4043, 0x63 },
> + { 0x5043, 0x63 },
> + { 0x6043, 0x63 },
> + { 0x7043, 0x63 },
> + { 0x8043, 0x63 },
> + { 0x9043, 0x63 },
> + { 0x20018, 0x3 },
> + { 0x20075, 0x4 },
> + { 0x20050, 0x0 },
> + { 0x20008, 0x2ee },
> + { 0x120008, 0x64 },
> + { 0x220008, 0x19 },
> + { 0x20088, 0x9 },
> + { 0x200b2, 0xdc },
> + { 0x10043, 0x5a1 },
> + { 0x10143, 0x5a1 },
> + { 0x11043, 0x5a1 },
> + { 0x11143, 0x5a1 },
> + { 0x12043, 0x5a1 },
> + { 0x12143, 0x5a1 },
> + { 0x13043, 0x5a1 },
> + { 0x13143, 0x5a1 },
> + { 0x1200b2, 0xdc },
> + { 0x110043, 0x5a1 },
> + { 0x110143, 0x5a1 },
> + { 0x111043, 0x5a1 },
> + { 0x111143, 0x5a1 },
> + { 0x112043, 0x5a1 },
> + { 0x112143, 0x5a1 },
> + { 0x113043, 0x5a1 },
> + { 0x113143, 0x5a1 },
> + { 0x2200b2, 0xdc },
> + { 0x210043, 0x5a1 },
> + { 0x210143, 0x5a1 },
> + { 0x211043, 0x5a1 },
> + { 0x211143, 0x5a1 },
> + { 0x212043, 0x5a1 },
> + { 0x212143, 0x5a1 },
> + { 0x213043, 0x5a1 },
> + { 0x213143, 0x5a1 },
> + { 0x200fa, 0x1 },
> + { 0x1200fa, 0x1 },
> + { 0x2200fa, 0x1 },
> + { 0x20019, 0x1 },
> + { 0x120019, 0x1 },
> + { 0x220019, 0x1 },
> + { 0x200f0, 0x660 },
> + { 0x200f1, 0x0 },
> + { 0x200f2, 0x4444 },
> + { 0x200f3, 0x8888 },
> + { 0x200f4, 0x5665 },
> + { 0x200f5, 0x0 },
> + { 0x200f6, 0x0 },
> + { 0x200f7, 0xf000 },
> + { 0x20025, 0x0 },
> + { 0x2002d, 0x0 },
> + { 0x12002d, 0x0 },
> + { 0x22002d, 0x0 },
> + { 0x200c7, 0x21 },
> + { 0x1200c7, 0x21 },
> + { 0x2200c7, 0x21 },
> + { 0x200ca, 0x24 },
> + { 0x1200ca, 0x24 },
> + { 0x2200ca, 0x24 },
> +};
> +
> +/* ddr phy trained csr */
> +static struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
> + { 0x200b2, 0x0 },
> + { 0x1200b2, 0x0 },
> + { 0x2200b2, 0x0 },
> + { 0x200cb, 0x0 },
> + { 0x10043, 0x0 },
> + { 0x110043, 0x0 },
> + { 0x210043, 0x0 },
> + { 0x10143, 0x0 },
> + { 0x110143, 0x0 },
> + { 0x210143, 0x0 },
> + { 0x11043, 0x0 },
> + { 0x111043, 0x0 },
> + { 0x211043, 0x0 },
> + { 0x11143, 0x0 },
> + { 0x111143, 0x0 },
> + { 0x211143, 0x0 },
> + { 0x12043, 0x0 },
> + { 0x112043, 0x0 },
> + { 0x212043, 0x0 },
> + { 0x12143, 0x0 },
> + { 0x112143, 0x0 },
> + { 0x212143, 0x0 },
> + { 0x13043, 0x0 },
> + { 0x113043, 0x0 },
> + { 0x213043, 0x0 },
> + { 0x13143, 0x0 },
> + { 0x113143, 0x0 },
> + { 0x213143, 0x0 },
> + { 0x80, 0x0 },
> + { 0x100080, 0x0 },
> + { 0x200080, 0x0 },
> + { 0x1080, 0x0 },
> + { 0x101080, 0x0 },
> + { 0x201080, 0x0 },
> + { 0x2080, 0x0 },
> + { 0x102080, 0x0 },
> + { 0x202080, 0x0 },
> + { 0x3080, 0x0 },
> + { 0x103080, 0x0 },
> + { 0x203080, 0x0 },
> + { 0x4080, 0x0 },
> + { 0x104080, 0x0 },
> + { 0x204080, 0x0 },
> + { 0x5080, 0x0 },
> + { 0x105080, 0x0 },
> + { 0x205080, 0x0 },
> + { 0x6080, 0x0 },
> + { 0x106080, 0x0 },
> + { 0x206080, 0x0 },
> + { 0x7080, 0x0 },
> + { 0x107080, 0x0 },
> + { 0x207080, 0x0 },
> + { 0x8080, 0x0 },
> + { 0x108080, 0x0 },
> + { 0x208080, 0x0 },
> + { 0x9080, 0x0 },
> + { 0x109080, 0x0 },
> + { 0x209080, 0x0 },
> + { 0x10080, 0x0 },
> + { 0x110080, 0x0 },
> + { 0x210080, 0x0 },
> + { 0x10180, 0x0 },
> + { 0x110180, 0x0 },
> + { 0x210180, 0x0 },
> + { 0x11080, 0x0 },
> + { 0x111080, 0x0 },
> + { 0x211080, 0x0 },
> + { 0x11180, 0x0 },
> + { 0x111180, 0x0 },
> + { 0x211180, 0x0 },
> + { 0x12080, 0x0 },
> + { 0x112080, 0x0 },
> + { 0x212080, 0x0 },
> + { 0x12180, 0x0 },
> + { 0x112180, 0x0 },
> + { 0x212180, 0x0 },
> + { 0x13080, 0x0 },
> + { 0x113080, 0x0 },
> + { 0x213080, 0x0 },
> + { 0x13180, 0x0 },
> + { 0x113180, 0x0 },
> + { 0x213180, 0x0 },
> + { 0x10081, 0x0 },
> + { 0x110081, 0x0 },
> + { 0x210081, 0x0 },
> + { 0x10181, 0x0 },
> + { 0x110181, 0x0 },
> + { 0x210181, 0x0 },
> + { 0x11081, 0x0 },
> + { 0x111081, 0x0 },
> + { 0x211081, 0x0 },
> + { 0x11181, 0x0 },
> + { 0x111181, 0x0 },
> + { 0x211181, 0x0 },
> + { 0x12081, 0x0 },
> + { 0x112081, 0x0 },
> + { 0x212081, 0x0 },
> + { 0x12181, 0x0 },
> + { 0x112181, 0x0 },
> + { 0x212181, 0x0 },
> + { 0x13081, 0x0 },
> + { 0x113081, 0x0 },
> + { 0x213081, 0x0 },
> + { 0x13181, 0x0 },
> + { 0x113181, 0x0 },
> + { 0x213181, 0x0 },
> + { 0x100d0, 0x0 },
> + { 0x1100d0, 0x0 },
> + { 0x2100d0, 0x0 },
> + { 0x101d0, 0x0 },
> + { 0x1101d0, 0x0 },
> + { 0x2101d0, 0x0 },
> + { 0x110d0, 0x0 },
> + { 0x1110d0, 0x0 },
> + { 0x2110d0, 0x0 },
> + { 0x111d0, 0x0 },
> + { 0x1111d0, 0x0 },
> + { 0x2111d0, 0x0 },
> + { 0x120d0, 0x0 },
> + { 0x1120d0, 0x0 },
> + { 0x2120d0, 0x0 },
> + { 0x121d0, 0x0 },
> + { 0x1121d0, 0x0 },
> + { 0x2121d0, 0x0 },
> + { 0x130d0, 0x0 },
> + { 0x1130d0, 0x0 },
> + { 0x2130d0, 0x0 },
> + { 0x131d0, 0x0 },
> + { 0x1131d0, 0x0 },
> + { 0x2131d0, 0x0 },
> + { 0x100d1, 0x0 },
> + { 0x1100d1, 0x0 },
> + { 0x2100d1, 0x0 },
> + { 0x101d1, 0x0 },
> + { 0x1101d1, 0x0 },
> + { 0x2101d1, 0x0 },
> + { 0x110d1, 0x0 },
> + { 0x1110d1, 0x0 },
> + { 0x2110d1, 0x0 },
> + { 0x111d1, 0x0 },
> + { 0x1111d1, 0x0 },
> + { 0x2111d1, 0x0 },
> + { 0x120d1, 0x0 },
> + { 0x1120d1, 0x0 },
> + { 0x2120d1, 0x0 },
> + { 0x121d1, 0x0 },
> + { 0x1121d1, 0x0 },
> + { 0x2121d1, 0x0 },
> + { 0x130d1, 0x0 },
> + { 0x1130d1, 0x0 },
> + { 0x2130d1, 0x0 },
> + { 0x131d1, 0x0 },
> + { 0x1131d1, 0x0 },
> + { 0x2131d1, 0x0 },
> + { 0x10068, 0x0 },
> + { 0x10168, 0x0 },
> + { 0x10268, 0x0 },
> + { 0x10368, 0x0 },
> + { 0x10468, 0x0 },
> + { 0x10568, 0x0 },
> + { 0x10668, 0x0 },
> + { 0x10768, 0x0 },
> + { 0x10868, 0x0 },
> + { 0x11068, 0x0 },
> + { 0x11168, 0x0 },
> + { 0x11268, 0x0 },
> + { 0x11368, 0x0 },
> + { 0x11468, 0x0 },
> + { 0x11568, 0x0 },
> + { 0x11668, 0x0 },
> + { 0x11768, 0x0 },
> + { 0x11868, 0x0 },
> + { 0x12068, 0x0 },
> + { 0x12168, 0x0 },
> + { 0x12268, 0x0 },
> + { 0x12368, 0x0 },
> + { 0x12468, 0x0 },
> + { 0x12568, 0x0 },
> + { 0x12668, 0x0 },
> + { 0x12768, 0x0 },
> + { 0x12868, 0x0 },
> + { 0x13068, 0x0 },
> + { 0x13168, 0x0 },
> + { 0x13268, 0x0 },
> + { 0x13368, 0x0 },
> + { 0x13468, 0x0 },
> + { 0x13568, 0x0 },
> + { 0x13668, 0x0 },
> + { 0x13768, 0x0 },
> + { 0x13868, 0x0 },
> + { 0x10069, 0x0 },
> + { 0x10169, 0x0 },
> + { 0x10269, 0x0 },
> + { 0x10369, 0x0 },
> + { 0x10469, 0x0 },
> + { 0x10569, 0x0 },
> + { 0x10669, 0x0 },
> + { 0x10769, 0x0 },
> + { 0x10869, 0x0 },
> + { 0x11069, 0x0 },
> + { 0x11169, 0x0 },
> + { 0x11269, 0x0 },
> + { 0x11369, 0x0 },
> + { 0x11469, 0x0 },
> + { 0x11569, 0x0 },
> + { 0x11669, 0x0 },
> + { 0x11769, 0x0 },
> + { 0x11869, 0x0 },
> + { 0x12069, 0x0 },
> + { 0x12169, 0x0 },
> + { 0x12269, 0x0 },
> + { 0x12369, 0x0 },
> + { 0x12469, 0x0 },
> + { 0x12569, 0x0 },
> + { 0x12669, 0x0 },
> + { 0x12769, 0x0 },
> + { 0x12869, 0x0 },
> + { 0x13069, 0x0 },
> + { 0x13169, 0x0 },
> + { 0x13269, 0x0 },
> + { 0x13369, 0x0 },
> + { 0x13469, 0x0 },
> + { 0x13569, 0x0 },
> + { 0x13669, 0x0 },
> + { 0x13769, 0x0 },
> + { 0x13869, 0x0 },
> + { 0x1008c, 0x0 },
> + { 0x11008c, 0x0 },
> + { 0x21008c, 0x0 },
> + { 0x1018c, 0x0 },
> + { 0x11018c, 0x0 },
> + { 0x21018c, 0x0 },
> + { 0x1108c, 0x0 },
> + { 0x11108c, 0x0 },
> + { 0x21108c, 0x0 },
> + { 0x1118c, 0x0 },
> + { 0x11118c, 0x0 },
> + { 0x21118c, 0x0 },
> + { 0x1208c, 0x0 },
> + { 0x11208c, 0x0 },
> + { 0x21208c, 0x0 },
> + { 0x1218c, 0x0 },
> + { 0x11218c, 0x0 },
> + { 0x21218c, 0x0 },
> + { 0x1308c, 0x0 },
> + { 0x11308c, 0x0 },
> + { 0x21308c, 0x0 },
> + { 0x1318c, 0x0 },
> + { 0x11318c, 0x0 },
> + { 0x21318c, 0x0 },
> + { 0x1008d, 0x0 },
> + { 0x11008d, 0x0 },
> + { 0x21008d, 0x0 },
> + { 0x1018d, 0x0 },
> + { 0x11018d, 0x0 },
> + { 0x21018d, 0x0 },
> + { 0x1108d, 0x0 },
> + { 0x11108d, 0x0 },
> + { 0x21108d, 0x0 },
> + { 0x1118d, 0x0 },
> + { 0x11118d, 0x0 },
> + { 0x21118d, 0x0 },
> + { 0x1208d, 0x0 },
> + { 0x11208d, 0x0 },
> + { 0x21208d, 0x0 },
> + { 0x1218d, 0x0 },
> + { 0x11218d, 0x0 },
> + { 0x21218d, 0x0 },
> + { 0x1308d, 0x0 },
> + { 0x11308d, 0x0 },
> + { 0x21308d, 0x0 },
> + { 0x1318d, 0x0 },
> + { 0x11318d, 0x0 },
> + { 0x21318d, 0x0 },
> + { 0x100c0, 0x0 },
> + { 0x1100c0, 0x0 },
> + { 0x2100c0, 0x0 },
> + { 0x101c0, 0x0 },
> + { 0x1101c0, 0x0 },
> + { 0x2101c0, 0x0 },
> + { 0x102c0, 0x0 },
> + { 0x1102c0, 0x0 },
> + { 0x2102c0, 0x0 },
> + { 0x103c0, 0x0 },
> + { 0x1103c0, 0x0 },
> + { 0x2103c0, 0x0 },
> + { 0x104c0, 0x0 },
> + { 0x1104c0, 0x0 },
> + { 0x2104c0, 0x0 },
> + { 0x105c0, 0x0 },
> + { 0x1105c0, 0x0 },
> + { 0x2105c0, 0x0 },
> + { 0x106c0, 0x0 },
> + { 0x1106c0, 0x0 },
> + { 0x2106c0, 0x0 },
> + { 0x107c0, 0x0 },
> + { 0x1107c0, 0x0 },
> + { 0x2107c0, 0x0 },
> + { 0x108c0, 0x0 },
> + { 0x1108c0, 0x0 },
> + { 0x2108c0, 0x0 },
> + { 0x110c0, 0x0 },
> + { 0x1110c0, 0x0 },
> + { 0x2110c0, 0x0 },
> + { 0x111c0, 0x0 },
> + { 0x1111c0, 0x0 },
> + { 0x2111c0, 0x0 },
> + { 0x112c0, 0x0 },
> + { 0x1112c0, 0x0 },
> + { 0x2112c0, 0x0 },
> + { 0x113c0, 0x0 },
> + { 0x1113c0, 0x0 },
> + { 0x2113c0, 0x0 },
> + { 0x114c0, 0x0 },
> + { 0x1114c0, 0x0 },
> + { 0x2114c0, 0x0 },
> + { 0x115c0, 0x0 },
> + { 0x1115c0, 0x0 },
> + { 0x2115c0, 0x0 },
> + { 0x116c0, 0x0 },
> + { 0x1116c0, 0x0 },
> + { 0x2116c0, 0x0 },
> + { 0x117c0, 0x0 },
> + { 0x1117c0, 0x0 },
> + { 0x2117c0, 0x0 },
> + { 0x118c0, 0x0 },
> + { 0x1118c0, 0x0 },
> + { 0x2118c0, 0x0 },
> + { 0x120c0, 0x0 },
> + { 0x1120c0, 0x0 },
> + { 0x2120c0, 0x0 },
> + { 0x121c0, 0x0 },
> + { 0x1121c0, 0x0 },
> + { 0x2121c0, 0x0 },
> + { 0x122c0, 0x0 },
> + { 0x1122c0, 0x0 },
> + { 0x2122c0, 0x0 },
> + { 0x123c0, 0x0 },
> + { 0x1123c0, 0x0 },
> + { 0x2123c0, 0x0 },
> + { 0x124c0, 0x0 },
> + { 0x1124c0, 0x0 },
> + { 0x2124c0, 0x0 },
> + { 0x125c0, 0x0 },
> + { 0x1125c0, 0x0 },
> + { 0x2125c0, 0x0 },
> + { 0x126c0, 0x0 },
> + { 0x1126c0, 0x0 },
> + { 0x2126c0, 0x0 },
> + { 0x127c0, 0x0 },
> + { 0x1127c0, 0x0 },
> + { 0x2127c0, 0x0 },
> + { 0x128c0, 0x0 },
> + { 0x1128c0, 0x0 },
> + { 0x2128c0, 0x0 },
> + { 0x130c0, 0x0 },
> + { 0x1130c0, 0x0 },
> + { 0x2130c0, 0x0 },
> + { 0x131c0, 0x0 },
> + { 0x1131c0, 0x0 },
> + { 0x2131c0, 0x0 },
> + { 0x132c0, 0x0 },
> + { 0x1132c0, 0x0 },
> + { 0x2132c0, 0x0 },
> + { 0x133c0, 0x0 },
> + { 0x1133c0, 0x0 },
> + { 0x2133c0, 0x0 },
> + { 0x134c0, 0x0 },
> + { 0x1134c0, 0x0 },
> + { 0x2134c0, 0x0 },
> + { 0x135c0, 0x0 },
> + { 0x1135c0, 0x0 },
> + { 0x2135c0, 0x0 },
> + { 0x136c0, 0x0 },
> + { 0x1136c0, 0x0 },
> + { 0x2136c0, 0x0 },
> + { 0x137c0, 0x0 },
> + { 0x1137c0, 0x0 },
> + { 0x2137c0, 0x0 },
> + { 0x138c0, 0x0 },
> + { 0x1138c0, 0x0 },
> + { 0x2138c0, 0x0 },
> + { 0x100c1, 0x0 },
> + { 0x1100c1, 0x0 },
> + { 0x2100c1, 0x0 },
> + { 0x101c1, 0x0 },
> + { 0x1101c1, 0x0 },
> + { 0x2101c1, 0x0 },
> + { 0x102c1, 0x0 },
> + { 0x1102c1, 0x0 },
> + { 0x2102c1, 0x0 },
> + { 0x103c1, 0x0 },
> + { 0x1103c1, 0x0 },
> + { 0x2103c1, 0x0 },
> + { 0x104c1, 0x0 },
> + { 0x1104c1, 0x0 },
> + { 0x2104c1, 0x0 },
> + { 0x105c1, 0x0 },
> + { 0x1105c1, 0x0 },
> + { 0x2105c1, 0x0 },
> + { 0x106c1, 0x0 },
> + { 0x1106c1, 0x0 },
> + { 0x2106c1, 0x0 },
> + { 0x107c1, 0x0 },
> + { 0x1107c1, 0x0 },
> + { 0x2107c1, 0x0 },
> + { 0x108c1, 0x0 },
> + { 0x1108c1, 0x0 },
> + { 0x2108c1, 0x0 },
> + { 0x110c1, 0x0 },
> + { 0x1110c1, 0x0 },
> + { 0x2110c1, 0x0 },
> + { 0x111c1, 0x0 },
> + { 0x1111c1, 0x0 },
> + { 0x2111c1, 0x0 },
> + { 0x112c1, 0x0 },
> + { 0x1112c1, 0x0 },
> + { 0x2112c1, 0x0 },
> + { 0x113c1, 0x0 },
> + { 0x1113c1, 0x0 },
> + { 0x2113c1, 0x0 },
> + { 0x114c1, 0x0 },
> + { 0x1114c1, 0x0 },
> + { 0x2114c1, 0x0 },
> + { 0x115c1, 0x0 },
> + { 0x1115c1, 0x0 },
> + { 0x2115c1, 0x0 },
> + { 0x116c1, 0x0 },
> + { 0x1116c1, 0x0 },
> + { 0x2116c1, 0x0 },
> + { 0x117c1, 0x0 },
> + { 0x1117c1, 0x0 },
> + { 0x2117c1, 0x0 },
> + { 0x118c1, 0x0 },
> + { 0x1118c1, 0x0 },
> + { 0x2118c1, 0x0 },
> + { 0x120c1, 0x0 },
> + { 0x1120c1, 0x0 },
> + { 0x2120c1, 0x0 },
> + { 0x121c1, 0x0 },
> + { 0x1121c1, 0x0 },
> + { 0x2121c1, 0x0 },
> + { 0x122c1, 0x0 },
> + { 0x1122c1, 0x0 },
> + { 0x2122c1, 0x0 },
> + { 0x123c1, 0x0 },
> + { 0x1123c1, 0x0 },
> + { 0x2123c1, 0x0 },
> + { 0x124c1, 0x0 },
> + { 0x1124c1, 0x0 },
> + { 0x2124c1, 0x0 },
> + { 0x125c1, 0x0 },
> + { 0x1125c1, 0x0 },
> + { 0x2125c1, 0x0 },
> + { 0x126c1, 0x0 },
> + { 0x1126c1, 0x0 },
> + { 0x2126c1, 0x0 },
> + { 0x127c1, 0x0 },
> + { 0x1127c1, 0x0 },
> + { 0x2127c1, 0x0 },
> + { 0x128c1, 0x0 },
> + { 0x1128c1, 0x0 },
> + { 0x2128c1, 0x0 },
> + { 0x130c1, 0x0 },
> + { 0x1130c1, 0x0 },
> + { 0x2130c1, 0x0 },
> + { 0x131c1, 0x0 },
> + { 0x1131c1, 0x0 },
> + { 0x2131c1, 0x0 },
> + { 0x132c1, 0x0 },
> + { 0x1132c1, 0x0 },
> + { 0x2132c1, 0x0 },
> + { 0x133c1, 0x0 },
> + { 0x1133c1, 0x0 },
> + { 0x2133c1, 0x0 },
> + { 0x134c1, 0x0 },
> + { 0x1134c1, 0x0 },
> + { 0x2134c1, 0x0 },
> + { 0x135c1, 0x0 },
> + { 0x1135c1, 0x0 },
> + { 0x2135c1, 0x0 },
> + { 0x136c1, 0x0 },
> + { 0x1136c1, 0x0 },
> + { 0x2136c1, 0x0 },
> + { 0x137c1, 0x0 },
> + { 0x1137c1, 0x0 },
> + { 0x2137c1, 0x0 },
> + { 0x138c1, 0x0 },
> + { 0x1138c1, 0x0 },
> + { 0x2138c1, 0x0 },
> + { 0x10020, 0x0 },
> + { 0x110020, 0x0 },
> + { 0x210020, 0x0 },
> + { 0x11020, 0x0 },
> + { 0x111020, 0x0 },
> + { 0x211020, 0x0 },
> + { 0x12020, 0x0 },
> + { 0x112020, 0x0 },
> + { 0x212020, 0x0 },
> + { 0x13020, 0x0 },
> + { 0x113020, 0x0 },
> + { 0x213020, 0x0 },
> + { 0x20072, 0x0 },
> + { 0x20073, 0x0 },
> + { 0x20074, 0x0 },
> + { 0x100aa, 0x0 },
> + { 0x110aa, 0x0 },
> + { 0x120aa, 0x0 },
> + { 0x130aa, 0x0 },
> + { 0x20010, 0x0 },
> + { 0x120010, 0x0 },
> + { 0x220010, 0x0 },
> + { 0x20011, 0x0 },
> + { 0x120011, 0x0 },
> + { 0x220011, 0x0 },
> + { 0x100ae, 0x0 },
> + { 0x1100ae, 0x0 },
> + { 0x2100ae, 0x0 },
> + { 0x100af, 0x0 },
> + { 0x1100af, 0x0 },
> + { 0x2100af, 0x0 },
> + { 0x110ae, 0x0 },
> + { 0x1110ae, 0x0 },
> + { 0x2110ae, 0x0 },
> + { 0x110af, 0x0 },
> + { 0x1110af, 0x0 },
> + { 0x2110af, 0x0 },
> + { 0x120ae, 0x0 },
> + { 0x1120ae, 0x0 },
> + { 0x2120ae, 0x0 },
> + { 0x120af, 0x0 },
> + { 0x1120af, 0x0 },
> + { 0x2120af, 0x0 },
> + { 0x130ae, 0x0 },
> + { 0x1130ae, 0x0 },
> + { 0x2130ae, 0x0 },
> + { 0x130af, 0x0 },
> + { 0x1130af, 0x0 },
> + { 0x2130af, 0x0 },
> + { 0x20020, 0x0 },
> + { 0x120020, 0x0 },
> + { 0x220020, 0x0 },
> + { 0x100a0, 0x0 },
> + { 0x100a1, 0x0 },
> + { 0x100a2, 0x0 },
> + { 0x100a3, 0x0 },
> + { 0x100a4, 0x0 },
> + { 0x100a5, 0x0 },
> + { 0x100a6, 0x0 },
> + { 0x100a7, 0x0 },
> + { 0x110a0, 0x0 },
> + { 0x110a1, 0x0 },
> + { 0x110a2, 0x0 },
> + { 0x110a3, 0x0 },
> + { 0x110a4, 0x0 },
> + { 0x110a5, 0x0 },
> + { 0x110a6, 0x0 },
> + { 0x110a7, 0x0 },
> + { 0x120a0, 0x0 },
> + { 0x120a1, 0x0 },
> + { 0x120a2, 0x0 },
> + { 0x120a3, 0x0 },
> + { 0x120a4, 0x0 },
> + { 0x120a5, 0x0 },
> + { 0x120a6, 0x0 },
> + { 0x120a7, 0x0 },
> + { 0x130a0, 0x0 },
> + { 0x130a1, 0x0 },
> + { 0x130a2, 0x0 },
> + { 0x130a3, 0x0 },
> + { 0x130a4, 0x0 },
> + { 0x130a5, 0x0 },
> + { 0x130a6, 0x0 },
> + { 0x130a7, 0x0 },
> + { 0x2007c, 0x0 },
> + { 0x12007c, 0x0 },
> + { 0x22007c, 0x0 },
> + { 0x2007d, 0x0 },
> + { 0x12007d, 0x0 },
> + { 0x22007d, 0x0 },
> + { 0x400fd, 0x0 },
> + { 0x400c0, 0x0 },
> + { 0x90201, 0x0 },
> + { 0x190201, 0x0 },
> + { 0x290201, 0x0 },
> + { 0x90202, 0x0 },
> + { 0x190202, 0x0 },
> + { 0x290202, 0x0 },
> + { 0x90203, 0x0 },
> + { 0x190203, 0x0 },
> + { 0x290203, 0x0 },
> + { 0x90204, 0x0 },
> + { 0x190204, 0x0 },
> + { 0x290204, 0x0 },
> + { 0x90205, 0x0 },
> + { 0x190205, 0x0 },
> + { 0x290205, 0x0 },
> + { 0x90206, 0x0 },
> + { 0x190206, 0x0 },
> + { 0x290206, 0x0 },
> + { 0x90207, 0x0 },
> + { 0x190207, 0x0 },
> + { 0x290207, 0x0 },
> + { 0x90208, 0x0 },
> + { 0x190208, 0x0 },
> + { 0x290208, 0x0 },
> + { 0x10062, 0x0 },
> + { 0x10162, 0x0 },
> + { 0x10262, 0x0 },
> + { 0x10362, 0x0 },
> + { 0x10462, 0x0 },
> + { 0x10562, 0x0 },
> + { 0x10662, 0x0 },
> + { 0x10762, 0x0 },
> + { 0x10862, 0x0 },
> + { 0x11062, 0x0 },
> + { 0x11162, 0x0 },
> + { 0x11262, 0x0 },
> + { 0x11362, 0x0 },
> + { 0x11462, 0x0 },
> + { 0x11562, 0x0 },
> + { 0x11662, 0x0 },
> + { 0x11762, 0x0 },
> + { 0x11862, 0x0 },
> + { 0x12062, 0x0 },
> + { 0x12162, 0x0 },
> + { 0x12262, 0x0 },
> + { 0x12362, 0x0 },
> + { 0x12462, 0x0 },
> + { 0x12562, 0x0 },
> + { 0x12662, 0x0 },
> + { 0x12762, 0x0 },
> + { 0x12862, 0x0 },
> + { 0x13062, 0x0 },
> + { 0x13162, 0x0 },
> + { 0x13262, 0x0 },
> + { 0x13362, 0x0 },
> + { 0x13462, 0x0 },
> + { 0x13562, 0x0 },
> + { 0x13662, 0x0 },
> + { 0x13762, 0x0 },
> + { 0x13862, 0x0 },
> + { 0x20077, 0x0 },
> + { 0x10001, 0x0 },
> + { 0x11001, 0x0 },
> + { 0x12001, 0x0 },
> + { 0x13001, 0x0 },
> + { 0x10040, 0x0 },
> + { 0x10140, 0x0 },
> + { 0x10240, 0x0 },
> + { 0x10340, 0x0 },
> + { 0x10440, 0x0 },
> + { 0x10540, 0x0 },
> + { 0x10640, 0x0 },
> + { 0x10740, 0x0 },
> + { 0x10840, 0x0 },
> + { 0x10030, 0x0 },
> + { 0x10130, 0x0 },
> + { 0x10230, 0x0 },
> + { 0x10330, 0x0 },
> + { 0x10430, 0x0 },
> + { 0x10530, 0x0 },
> + { 0x10630, 0x0 },
> + { 0x10730, 0x0 },
> + { 0x10830, 0x0 },
> + { 0x11040, 0x0 },
> + { 0x11140, 0x0 },
> + { 0x11240, 0x0 },
> + { 0x11340, 0x0 },
> + { 0x11440, 0x0 },
> + { 0x11540, 0x0 },
> + { 0x11640, 0x0 },
> + { 0x11740, 0x0 },
> + { 0x11840, 0x0 },
> + { 0x11030, 0x0 },
> + { 0x11130, 0x0 },
> + { 0x11230, 0x0 },
> + { 0x11330, 0x0 },
> + { 0x11430, 0x0 },
> + { 0x11530, 0x0 },
> + { 0x11630, 0x0 },
> + { 0x11730, 0x0 },
> + { 0x11830, 0x0 },
> + { 0x12040, 0x0 },
> + { 0x12140, 0x0 },
> + { 0x12240, 0x0 },
> + { 0x12340, 0x0 },
> + { 0x12440, 0x0 },
> + { 0x12540, 0x0 },
> + { 0x12640, 0x0 },
> + { 0x12740, 0x0 },
> + { 0x12840, 0x0 },
> + { 0x12030, 0x0 },
> + { 0x12130, 0x0 },
> + { 0x12230, 0x0 },
> + { 0x12330, 0x0 },
> + { 0x12430, 0x0 },
> + { 0x12530, 0x0 },
> + { 0x12630, 0x0 },
> + { 0x12730, 0x0 },
> + { 0x12830, 0x0 },
> + { 0x13040, 0x0 },
> + { 0x13140, 0x0 },
> + { 0x13240, 0x0 },
> + { 0x13340, 0x0 },
> + { 0x13440, 0x0 },
> + { 0x13540, 0x0 },
> + { 0x13640, 0x0 },
> + { 0x13740, 0x0 },
> + { 0x13840, 0x0 },
> + { 0x13030, 0x0 },
> + { 0x13130, 0x0 },
> + { 0x13230, 0x0 },
> + { 0x13330, 0x0 },
> + { 0x13430, 0x0 },
> + { 0x13530, 0x0 },
> + { 0x13630, 0x0 },
> + { 0x13730, 0x0 },
> + { 0x13830, 0x0 },
> +};
> +
> +/* P0 message block paremeter for training firmware */
> +static struct dram_cfg_param ddr_fsp0_cfg[] = {
> + { 0xd0000, 0x0 },
> + { 0x54003, 0xbb8 },
> + { 0x54004, 0x2 },
> + { 0x54005, 0x2228 },
> + { 0x54006, 0x11 },
> + { 0x54008, 0x131f },
> + { 0x54009, 0xc8 },
> + { 0x5400b, 0x2 },
> + { 0x54012, 0x110 },
> + { 0x54019, 0x2dd4 },
> + { 0x5401a, 0x31 },
> + { 0x5401b, 0x4d66 },
> + { 0x5401c, 0x4d00 },
> + { 0x5401e, 0x16 },
> + { 0x5401f, 0x2dd4 },
> + { 0x54020, 0x31 },
> + { 0x54021, 0x4d66 },
> + { 0x54022, 0x4d00 },
> + { 0x54024, 0x16 },
> + { 0x5402b, 0x1000 },
> + { 0x5402c, 0x1 },
> + { 0x54032, 0xd400 },
> + { 0x54033, 0x312d },
> + { 0x54034, 0x6600 },
> + { 0x54035, 0x4d },
> + { 0x54036, 0x4d },
> + { 0x54037, 0x1600 },
> + { 0x54038, 0xd400 },
> + { 0x54039, 0x312d },
> + { 0x5403a, 0x6600 },
> + { 0x5403b, 0x4d },
> + { 0x5403c, 0x4d },
> + { 0x5403d, 0x1600 },
> + { 0xd0000, 0x1 },
> +};
> +
> +/* P1 message block paremeter for training firmware */
> +static struct dram_cfg_param ddr_fsp1_cfg[] = {
> + { 0xd0000, 0x0 },
> + { 0x54002, 0x101 },
> + { 0x54003, 0x190 },
> + { 0x54004, 0x2 },
> + { 0x54005, 0x2228 },
> + { 0x54006, 0x11 },
> + { 0x54008, 0x121f },
> + { 0x54009, 0xc8 },
> + { 0x5400b, 0x2 },
> + { 0x54012, 0x110 },
> + { 0x54019, 0x84 },
> + { 0x5401a, 0x31 },
> + { 0x5401b, 0x4d66 },
> + { 0x5401c, 0x4d00 },
> + { 0x5401e, 0x16 },
> + { 0x5401f, 0x84 },
> + { 0x54020, 0x31 },
> + { 0x54021, 0x4d66 },
> + { 0x54022, 0x4d00 },
> + { 0x54024, 0x16 },
> + { 0x5402b, 0x1000 },
> + { 0x5402c, 0x1 },
> + { 0x54032, 0x8400 },
> + { 0x54033, 0x3100 },
> + { 0x54034, 0x6600 },
> + { 0x54035, 0x4d },
> + { 0x54036, 0x4d },
> + { 0x54037, 0x1600 },
> + { 0x54038, 0x8400 },
> + { 0x54039, 0x3100 },
> + { 0x5403a, 0x6600 },
> + { 0x5403b, 0x4d },
> + { 0x5403c, 0x4d },
> + { 0x5403d, 0x1600 },
> + { 0xd0000, 0x1 },
> +};
> +
> +/* P2 message block paremeter for training firmware */
> +static struct dram_cfg_param ddr_fsp2_cfg[] = {
> + { 0xd0000, 0x0 },
> + { 0x54002, 0x102 },
> + { 0x54003, 0x64 },
> + { 0x54004, 0x2 },
> + { 0x54005, 0x2228 },
> + { 0x54006, 0x11 },
> + { 0x54008, 0x121f },
> + { 0x54009, 0xc8 },
> + { 0x5400b, 0x2 },
> + { 0x54012, 0x110 },
> + { 0x54019, 0x84 },
> + { 0x5401a, 0x31 },
> + { 0x5401b, 0x4d66 },
> + { 0x5401c, 0x4d00 },
> + { 0x5401e, 0x16 },
> + { 0x5401f, 0x84 },
> + { 0x54020, 0x31 },
> + { 0x54021, 0x4d66 },
> + { 0x54022, 0x4d00 },
> + { 0x54024, 0x16 },
> + { 0x5402b, 0x1000 },
> + { 0x5402c, 0x1 },
> + { 0x54032, 0x8400 },
> + { 0x54033, 0x3100 },
> + { 0x54034, 0x6600 },
> + { 0x54035, 0x4d },
> + { 0x54036, 0x4d },
> + { 0x54037, 0x1600 },
> + { 0x54038, 0x8400 },
> + { 0x54039, 0x3100 },
> + { 0x5403a, 0x6600 },
> + { 0x5403b, 0x4d },
> + { 0x5403c, 0x4d },
> + { 0x5403d, 0x1600 },
> + { 0xd0000, 0x1 },
> +};
> +
> +/* P0 2D message block paremeter for training firmware */
> +static struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
> + { 0xd0000, 0x0 },
> + { 0x54003, 0xbb8 },
> + { 0x54004, 0x2 },
> + { 0x54005, 0x2228 },
> + { 0x54006, 0x11 },
> + { 0x54008, 0x61 },
> + { 0x54009, 0xc8 },
> + { 0x5400b, 0x2 },
> + { 0x5400f, 0x100 },
> + { 0x54010, 0x1f7f },
> + { 0x54012, 0x110 },
> + { 0x54019, 0x2dd4 },
> + { 0x5401a, 0x31 },
> + { 0x5401b, 0x4d66 },
> + { 0x5401c, 0x4d00 },
> + { 0x5401e, 0x16 },
> + { 0x5401f, 0x2dd4 },
> + { 0x54020, 0x31 },
> + { 0x54021, 0x4d66 },
> + { 0x54022, 0x4d00 },
> + { 0x54024, 0x16 },
> + { 0x5402b, 0x1000 },
> + { 0x5402c, 0x1 },
> + { 0x54032, 0xd400 },
> + { 0x54033, 0x312d },
> + { 0x54034, 0x6600 },
> + { 0x54035, 0x4d },
> + { 0x54036, 0x4d },
> + { 0x54037, 0x1600 },
> + { 0x54038, 0xd400 },
> + { 0x54039, 0x312d },
> + { 0x5403a, 0x6600 },
> + { 0x5403b, 0x4d },
> + { 0x5403c, 0x4d },
> + { 0x5403d, 0x1600 },
> + { 0xd0000, 0x1 },
> +};
> +
> +/* DRAM PHY init engine image */
> +static struct dram_cfg_param ddr_phy_pie[] = {
> + { 0xd0000, 0x0 },
> + { 0x90000, 0x10 },
> + { 0x90001, 0x400 },
> + { 0x90002, 0x10e },
> + { 0x90003, 0x0 },
> + { 0x90004, 0x0 },
> + { 0x90005, 0x8 },
> + { 0x90029, 0xb },
> + { 0x9002a, 0x480 },
> + { 0x9002b, 0x109 },
> + { 0x9002c, 0x8 },
> + { 0x9002d, 0x448 },
> + { 0x9002e, 0x139 },
> + { 0x9002f, 0x8 },
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> + { 0x123b4, 0x1 },
> + { 0x124b4, 0x1 },
> + { 0x125b4, 0x1 },
> + { 0x126b4, 0x1 },
> + { 0x127b4, 0x1 },
> + { 0x128b4, 0x1 },
> + { 0x13011, 0x1 },
> + { 0x13012, 0x1 },
> + { 0x13013, 0x180 },
> + { 0x13018, 0x1 },
> + { 0x13002, 0x6209 },
> + { 0x130b2, 0x1 },
> + { 0x131b4, 0x1 },
> + { 0x132b4, 0x1 },
> + { 0x133b4, 0x1 },
> + { 0x134b4, 0x1 },
> + { 0x135b4, 0x1 },
> + { 0x136b4, 0x1 },
> + { 0x137b4, 0x1 },
> + { 0x138b4, 0x1 },
> + { 0x2003a, 0x2 },
> + { 0xc0080, 0x2 },
> + { 0xd0000, 0x1 }
> +};
> +
> +static struct dram_fsp_msg ddr_dram_fsp_msg[] = {
> + {
> + /* P0 3000mts 1D */
> + .drate = 3000,
> + .fw_type = FW_1D_IMAGE,
> + .fsp_cfg = ddr_fsp0_cfg,
> + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
> + },
> + {
> + /* P1 400mts 1D */
> + .drate = 400,
> + .fw_type = FW_1D_IMAGE,
> + .fsp_cfg = ddr_fsp1_cfg,
> + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
> + },
> + {
> + /* P2 100mts 1D */
> + .drate = 100,
> + .fw_type = FW_1D_IMAGE,
> + .fsp_cfg = ddr_fsp2_cfg,
> + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
> + },
> + {
> + /* P0 3000mts 2D */
> + .drate = 3000,
> + .fw_type = FW_2D_IMAGE,
> + .fsp_cfg = ddr_fsp0_2d_cfg,
> + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
> + },
> +};
> +
> +/* ddr timing config params */
> +struct dram_timing_info dmo_imx8mm_sbc_dram_timing_16_32 = {
> + .ddrc_cfg = ddr_ddrc_cfg,
> + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
> + .ddrphy_cfg = ddr_ddrphy_cfg,
> + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
> + .fsp_msg = ddr_dram_fsp_msg,
> + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
> + .ddrphy_trained_csr = ddr_ddrphy_trained_csr,
> + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
> + .ddrphy_pie = ddr_phy_pie,
> + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
> + .fsp_table = { 3000, 400, 100, },
> +};
> diff --git a/board/data_modul/imx8mm_edm_sbc/lpddr4_timing_4G_32.c b/board/data_modul/imx8mm_edm_sbc/lpddr4_timing_4G_32.c
> new file mode 100644
> index 00000000000..e44c1ea2772
> --- /dev/null
> +++ b/board/data_modul/imx8mm_edm_sbc/lpddr4_timing_4G_32.c
> @@ -0,0 +1,1842 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2019 NXP
> + *
> + * Generated code from MX8M_DDR_tool
> + * Align with uboot version:
> + * imx_v2018.03_4.14.78_1.0.0_ga ~ imx_v2018.04_4.19.35_1.0.0_ga
> + */
> +
> +#include <linux/kernel.h>
> +#include <asm/arch/ddr.h>
> +
> +static struct dram_cfg_param ddr_ddrc_cfg[] = {
> + /** Initialize DDRC registers **/
> + { 0x3d400304, 0x1 },
> + { 0x3d400030, 0x1 },
> + { 0x3d400000, 0xa3080020 },
> + { 0x3d400020, 0x203 },
> + { 0x3d400024, 0x3a980 },
> + { 0x3d400064, 0x5b00d2 },
> + { 0x3d4000d0, 0xc00305ba },
> + { 0x3d4000d4, 0x940000 },
> + { 0x3d4000dc, 0xd4002d },
> + { 0x3d4000e0, 0x310000 },
> + { 0x3d4000e8, 0x66004d },
> + { 0x3d4000ec, 0x16004d },
> + { 0x3d400100, 0x191e1920 },
> + { 0x3d400104, 0x60630 },
> + { 0x3d40010c, 0xb0b000 },
> + { 0x3d400110, 0xe04080e },
> + { 0x3d400114, 0x2040c0c },
> + { 0x3d400118, 0x1010007 },
> + { 0x3d40011c, 0x401 },
> + { 0x3d400130, 0x20600 },
> + { 0x3d400134, 0xc100002 },
> + { 0x3d400138, 0xd8 },
> + { 0x3d400144, 0x96004b },
> + { 0x3d400180, 0x2ee0017 },
> + { 0x3d400184, 0x2605b8e },
> + { 0x3d400188, 0x0 },
> + { 0x3d400190, 0x497820a },
> + { 0x3d400194, 0x80303 },
> + { 0x3d4001b4, 0x170a },
> + { 0x3d4001a0, 0xe0400018 },
> + { 0x3d4001a4, 0xdf00e4 },
> + { 0x3d4001a8, 0x80000000 },
> + { 0x3d4001b0, 0x11 },
> + { 0x3d4001c0, 0x1 },
> + { 0x3d4001c4, 0x1 },
> + { 0x3d4000f4, 0xc99 },
> + { 0x3d400108, 0x70e1617 },
> + { 0x3d400200, 0x17 },
> + { 0x3d40020c, 0x0 },
> + { 0x3d400210, 0x1f1f },
> + { 0x3d400204, 0x80808 },
> + { 0x3d400214, 0x7070707 },
> + { 0x3d400218, 0x7070707 },
> + { 0x3d400250, 0x29001701 },
> + { 0x3d400254, 0x2c },
> + { 0x3d40025c, 0x4000030 },
> + { 0x3d400264, 0x900093e7 },
> + { 0x3d40026c, 0x2005574 },
> + { 0x3d400400, 0x111 },
> + { 0x3d400408, 0x72ff },
> + { 0x3d400494, 0x2100e07 },
> + { 0x3d400498, 0x620096 },
> + { 0x3d40049c, 0x1100e07 },
> + { 0x3d4004a0, 0xc8012c },
> + { 0x3d402020, 0x1 },
> + { 0x3d402024, 0x7d00 },
> + { 0x3d402050, 0x20d040 },
> + { 0x3d402064, 0xc001c },
> + { 0x3d4020dc, 0x840000 },
> + { 0x3d4020e0, 0x310000 },
> + { 0x3d4020e8, 0x66004d },
> + { 0x3d4020ec, 0x16004d },
> + { 0x3d402100, 0xa040305 },
> + { 0x3d402104, 0x30407 },
> + { 0x3d402108, 0x203060b },
> + { 0x3d40210c, 0x505000 },
> + { 0x3d402110, 0x2040202 },
> + { 0x3d402114, 0x2030202 },
> + { 0x3d402118, 0x1010004 },
> + { 0x3d40211c, 0x301 },
> + { 0x3d402130, 0x20300 },
> + { 0x3d402134, 0xa100002 },
> + { 0x3d402138, 0x1d },
> + { 0x3d402144, 0x14000a },
> + { 0x3d402180, 0x640004 },
> + { 0x3d402190, 0x3818200 },
> + { 0x3d402194, 0x80303 },
> + { 0x3d4021b4, 0x100 },
> + { 0x3d4020f4, 0xc99 },
> + { 0x3d403020, 0x1 },
> + { 0x3d403024, 0x1f40 },
> + { 0x3d403050, 0x20d040 },
> + { 0x3d403064, 0x30007 },
> + { 0x3d4030dc, 0x840000 },
> + { 0x3d4030e0, 0x310000 },
> + { 0x3d4030e8, 0x66004d },
> + { 0x3d4030ec, 0x16004d },
> + { 0x3d403100, 0xa010102 },
> + { 0x3d403104, 0x30404 },
> + { 0x3d403108, 0x203060b },
> + { 0x3d40310c, 0x505000 },
> + { 0x3d403110, 0x2040202 },
> + { 0x3d403114, 0x2030202 },
> + { 0x3d403118, 0x1010004 },
> + { 0x3d40311c, 0x301 },
> + { 0x3d403130, 0x20300 },
> + { 0x3d403134, 0xa100002 },
> + { 0x3d403138, 0x8 },
> + { 0x3d403144, 0x50003 },
> + { 0x3d403180, 0x190004 },
> + { 0x3d403190, 0x3818200 },
> + { 0x3d403194, 0x80303 },
> + { 0x3d4031b4, 0x100 },
> + { 0x3d4030f4, 0xc99 },
> + { 0x3d400028, 0x0 },
> +};
> +
> +/* PHY Initialize Configuration */
> +static struct dram_cfg_param ddr_ddrphy_cfg[] = {
> + { 0x100a0, 0x6 },
> + { 0x100a1, 0x7 },
> + { 0x100a2, 0x0 },
> + { 0x100a3, 0x1 },
> + { 0x100a4, 0x3 },
> + { 0x100a5, 0x2 },
> + { 0x100a6, 0x4 },
> + { 0x100a7, 0x5 },
> + { 0x110a0, 0x0 },
> + { 0x110a1, 0x1 },
> + { 0x110a2, 0x5 },
> + { 0x110a3, 0x3 },
> + { 0x110a4, 0x2 },
> + { 0x110a5, 0x4 },
> + { 0x110a6, 0x6 },
> + { 0x110a7, 0x7 },
> + { 0x120a0, 0x0 },
> + { 0x120a1, 0x1 },
> + { 0x120a2, 0x5 },
> + { 0x120a3, 0x3 },
> + { 0x120a4, 0x2 },
> + { 0x120a5, 0x4 },
> + { 0x120a6, 0x6 },
> + { 0x120a7, 0x7 },
> + { 0x130a0, 0x6 },
> + { 0x130a1, 0x7 },
> + { 0x130a2, 0x0 },
> + { 0x130a3, 0x1 },
> + { 0x130a4, 0x3 },
> + { 0x130a5, 0x2 },
> + { 0x130a6, 0x4 },
> + { 0x130a7, 0x5 },
> + { 0x1005f, 0x1ff },
> + { 0x1015f, 0x1ff },
> + { 0x1105f, 0x1ff },
> + { 0x1115f, 0x1ff },
> + { 0x1205f, 0x1ff },
> + { 0x1215f, 0x1ff },
> + { 0x1305f, 0x1ff },
> + { 0x1315f, 0x1ff },
> + { 0x11005f, 0x1ff },
> + { 0x11015f, 0x1ff },
> + { 0x11105f, 0x1ff },
> + { 0x11115f, 0x1ff },
> + { 0x11205f, 0x1ff },
> + { 0x11215f, 0x1ff },
> + { 0x11305f, 0x1ff },
> + { 0x11315f, 0x1ff },
> + { 0x21005f, 0x1ff },
> + { 0x21015f, 0x1ff },
> + { 0x21105f, 0x1ff },
> + { 0x21115f, 0x1ff },
> + { 0x21205f, 0x1ff },
> + { 0x21215f, 0x1ff },
> + { 0x21305f, 0x1ff },
> + { 0x21315f, 0x1ff },
> + { 0x55, 0x1ff },
> + { 0x1055, 0x1ff },
> + { 0x2055, 0x1ff },
> + { 0x3055, 0x1ff },
> + { 0x4055, 0x1ff },
> + { 0x5055, 0x1ff },
> + { 0x6055, 0x1ff },
> + { 0x7055, 0x1ff },
> + { 0x8055, 0x1ff },
> + { 0x9055, 0x1ff },
> + { 0x200c5, 0x19 },
> + { 0x1200c5, 0x7 },
> + { 0x2200c5, 0x7 },
> + { 0x2002e, 0x2 },
> + { 0x12002e, 0x2 },
> + { 0x22002e, 0x2 },
> + { 0x90204, 0x0 },
> + { 0x190204, 0x0 },
> + { 0x290204, 0x0 },
> + { 0x20024, 0x1ab },
> + { 0x2003a, 0x0 },
> + { 0x120024, 0x1ab },
> + { 0x2003a, 0x0 },
> + { 0x220024, 0x1ab },
> + { 0x2003a, 0x0 },
> + { 0x20056, 0x3 },
> + { 0x120056, 0x3 },
> + { 0x220056, 0x3 },
> + { 0x1004d, 0xe00 },
> + { 0x1014d, 0xe00 },
> + { 0x1104d, 0xe00 },
> + { 0x1114d, 0xe00 },
> + { 0x1204d, 0xe00 },
> + { 0x1214d, 0xe00 },
> + { 0x1304d, 0xe00 },
> + { 0x1314d, 0xe00 },
> + { 0x11004d, 0xe00 },
> + { 0x11014d, 0xe00 },
> + { 0x11104d, 0xe00 },
> + { 0x11114d, 0xe00 },
> + { 0x11204d, 0xe00 },
> + { 0x11214d, 0xe00 },
> + { 0x11304d, 0xe00 },
> + { 0x11314d, 0xe00 },
> + { 0x21004d, 0xe00 },
> + { 0x21014d, 0xe00 },
> + { 0x21104d, 0xe00 },
> + { 0x21114d, 0xe00 },
> + { 0x21204d, 0xe00 },
> + { 0x21214d, 0xe00 },
> + { 0x21304d, 0xe00 },
> + { 0x21314d, 0xe00 },
> + { 0x10049, 0xeba },
> + { 0x10149, 0xeba },
> + { 0x11049, 0xeba },
> + { 0x11149, 0xeba },
> + { 0x12049, 0xeba },
> + { 0x12149, 0xeba },
> + { 0x13049, 0xeba },
> + { 0x13149, 0xeba },
> + { 0x110049, 0xeba },
> + { 0x110149, 0xeba },
> + { 0x111049, 0xeba },
> + { 0x111149, 0xeba },
> + { 0x112049, 0xeba },
> + { 0x112149, 0xeba },
> + { 0x113049, 0xeba },
> + { 0x113149, 0xeba },
> + { 0x210049, 0xeba },
> + { 0x210149, 0xeba },
> + { 0x211049, 0xeba },
> + { 0x211149, 0xeba },
> + { 0x212049, 0xeba },
> + { 0x212149, 0xeba },
> + { 0x213049, 0xeba },
> + { 0x213149, 0xeba },
> + { 0x43, 0x63 },
> + { 0x1043, 0x63 },
> + { 0x2043, 0x63 },
> + { 0x3043, 0x63 },
> + { 0x4043, 0x63 },
> + { 0x5043, 0x63 },
> + { 0x6043, 0x63 },
> + { 0x7043, 0x63 },
> + { 0x8043, 0x63 },
> + { 0x9043, 0x63 },
> + { 0x20018, 0x3 },
> + { 0x20075, 0x4 },
> + { 0x20050, 0x0 },
> + { 0x20008, 0x2ee },
> + { 0x120008, 0x64 },
> + { 0x220008, 0x19 },
> + { 0x20088, 0x9 },
> + { 0x200b2, 0xdc },
> + { 0x10043, 0x5a1 },
> + { 0x10143, 0x5a1 },
> + { 0x11043, 0x5a1 },
> + { 0x11143, 0x5a1 },
> + { 0x12043, 0x5a1 },
> + { 0x12143, 0x5a1 },
> + { 0x13043, 0x5a1 },
> + { 0x13143, 0x5a1 },
> + { 0x1200b2, 0xdc },
> + { 0x110043, 0x5a1 },
> + { 0x110143, 0x5a1 },
> + { 0x111043, 0x5a1 },
> + { 0x111143, 0x5a1 },
> + { 0x112043, 0x5a1 },
> + { 0x112143, 0x5a1 },
> + { 0x113043, 0x5a1 },
> + { 0x113143, 0x5a1 },
> + { 0x2200b2, 0xdc },
> + { 0x210043, 0x5a1 },
> + { 0x210143, 0x5a1 },
> + { 0x211043, 0x5a1 },
> + { 0x211143, 0x5a1 },
> + { 0x212043, 0x5a1 },
> + { 0x212143, 0x5a1 },
> + { 0x213043, 0x5a1 },
> + { 0x213143, 0x5a1 },
> + { 0x200fa, 0x1 },
> + { 0x1200fa, 0x1 },
> + { 0x2200fa, 0x1 },
> + { 0x20019, 0x1 },
> + { 0x120019, 0x1 },
> + { 0x220019, 0x1 },
> + { 0x200f0, 0x660 },
> + { 0x200f1, 0x0 },
> + { 0x200f2, 0x4444 },
> + { 0x200f3, 0x8888 },
> + { 0x200f4, 0x5665 },
> + { 0x200f5, 0x0 },
> + { 0x200f6, 0x0 },
> + { 0x200f7, 0xf000 },
> + { 0x20025, 0x0 },
> + { 0x2002d, 0x0 },
> + { 0x12002d, 0x0 },
> + { 0x22002d, 0x0 },
> + { 0x200c7, 0x21 },
> + { 0x1200c7, 0x21 },
> + { 0x2200c7, 0x21 },
> + { 0x200ca, 0x24 },
> + { 0x1200ca, 0x24 },
> + { 0x2200ca, 0x24 },
> +};
> +
> +/* ddr phy trained csr */
> +static struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
> + { 0x200b2, 0x0 },
> + { 0x1200b2, 0x0 },
> + { 0x2200b2, 0x0 },
> + { 0x200cb, 0x0 },
> + { 0x10043, 0x0 },
> + { 0x110043, 0x0 },
> + { 0x210043, 0x0 },
> + { 0x10143, 0x0 },
> + { 0x110143, 0x0 },
> + { 0x210143, 0x0 },
> + { 0x11043, 0x0 },
> + { 0x111043, 0x0 },
> + { 0x211043, 0x0 },
> + { 0x11143, 0x0 },
> + { 0x111143, 0x0 },
> + { 0x211143, 0x0 },
> + { 0x12043, 0x0 },
> + { 0x112043, 0x0 },
> + { 0x212043, 0x0 },
> + { 0x12143, 0x0 },
> + { 0x112143, 0x0 },
> + { 0x212143, 0x0 },
> + { 0x13043, 0x0 },
> + { 0x113043, 0x0 },
> + { 0x213043, 0x0 },
> + { 0x13143, 0x0 },
> + { 0x113143, 0x0 },
> + { 0x213143, 0x0 },
> + { 0x80, 0x0 },
> + { 0x100080, 0x0 },
> + { 0x200080, 0x0 },
> + { 0x1080, 0x0 },
> + { 0x101080, 0x0 },
> + { 0x201080, 0x0 },
> + { 0x2080, 0x0 },
> + { 0x102080, 0x0 },
> + { 0x202080, 0x0 },
> + { 0x3080, 0x0 },
> + { 0x103080, 0x0 },
> + { 0x203080, 0x0 },
> + { 0x4080, 0x0 },
> + { 0x104080, 0x0 },
> + { 0x204080, 0x0 },
> + { 0x5080, 0x0 },
> + { 0x105080, 0x0 },
> + { 0x205080, 0x0 },
> + { 0x6080, 0x0 },
> + { 0x106080, 0x0 },
> + { 0x206080, 0x0 },
> + { 0x7080, 0x0 },
> + { 0x107080, 0x0 },
> + { 0x207080, 0x0 },
> + { 0x8080, 0x0 },
> + { 0x108080, 0x0 },
> + { 0x208080, 0x0 },
> + { 0x9080, 0x0 },
> + { 0x109080, 0x0 },
> + { 0x209080, 0x0 },
> + { 0x10080, 0x0 },
> + { 0x110080, 0x0 },
> + { 0x210080, 0x0 },
> + { 0x10180, 0x0 },
> + { 0x110180, 0x0 },
> + { 0x210180, 0x0 },
> + { 0x11080, 0x0 },
> + { 0x111080, 0x0 },
> + { 0x211080, 0x0 },
> + { 0x11180, 0x0 },
> + { 0x111180, 0x0 },
> + { 0x211180, 0x0 },
> + { 0x12080, 0x0 },
> + { 0x112080, 0x0 },
> + { 0x212080, 0x0 },
> + { 0x12180, 0x0 },
> + { 0x112180, 0x0 },
> + { 0x212180, 0x0 },
> + { 0x13080, 0x0 },
> + { 0x113080, 0x0 },
> + { 0x213080, 0x0 },
> + { 0x13180, 0x0 },
> + { 0x113180, 0x0 },
> + { 0x213180, 0x0 },
> + { 0x10081, 0x0 },
> + { 0x110081, 0x0 },
> + { 0x210081, 0x0 },
> + { 0x10181, 0x0 },
> + { 0x110181, 0x0 },
> + { 0x210181, 0x0 },
> + { 0x11081, 0x0 },
> + { 0x111081, 0x0 },
> + { 0x211081, 0x0 },
> + { 0x11181, 0x0 },
> + { 0x111181, 0x0 },
> + { 0x211181, 0x0 },
> + { 0x12081, 0x0 },
> + { 0x112081, 0x0 },
> + { 0x212081, 0x0 },
> + { 0x12181, 0x0 },
> + { 0x112181, 0x0 },
> + { 0x212181, 0x0 },
> + { 0x13081, 0x0 },
> + { 0x113081, 0x0 },
> + { 0x213081, 0x0 },
> + { 0x13181, 0x0 },
> + { 0x113181, 0x0 },
> + { 0x213181, 0x0 },
> + { 0x100d0, 0x0 },
> + { 0x1100d0, 0x0 },
> + { 0x2100d0, 0x0 },
> + { 0x101d0, 0x0 },
> + { 0x1101d0, 0x0 },
> + { 0x2101d0, 0x0 },
> + { 0x110d0, 0x0 },
> + { 0x1110d0, 0x0 },
> + { 0x2110d0, 0x0 },
> + { 0x111d0, 0x0 },
> + { 0x1111d0, 0x0 },
> + { 0x2111d0, 0x0 },
> + { 0x120d0, 0x0 },
> + { 0x1120d0, 0x0 },
> + { 0x2120d0, 0x0 },
> + { 0x121d0, 0x0 },
> + { 0x1121d0, 0x0 },
> + { 0x2121d0, 0x0 },
> + { 0x130d0, 0x0 },
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> + { 0x11440, 0x0 },
> + { 0x11540, 0x0 },
> + { 0x11640, 0x0 },
> + { 0x11740, 0x0 },
> + { 0x11840, 0x0 },
> + { 0x11030, 0x0 },
> + { 0x11130, 0x0 },
> + { 0x11230, 0x0 },
> + { 0x11330, 0x0 },
> + { 0x11430, 0x0 },
> + { 0x11530, 0x0 },
> + { 0x11630, 0x0 },
> + { 0x11730, 0x0 },
> + { 0x11830, 0x0 },
> + { 0x12040, 0x0 },
> + { 0x12140, 0x0 },
> + { 0x12240, 0x0 },
> + { 0x12340, 0x0 },
> + { 0x12440, 0x0 },
> + { 0x12540, 0x0 },
> + { 0x12640, 0x0 },
> + { 0x12740, 0x0 },
> + { 0x12840, 0x0 },
> + { 0x12030, 0x0 },
> + { 0x12130, 0x0 },
> + { 0x12230, 0x0 },
> + { 0x12330, 0x0 },
> + { 0x12430, 0x0 },
> + { 0x12530, 0x0 },
> + { 0x12630, 0x0 },
> + { 0x12730, 0x0 },
> + { 0x12830, 0x0 },
> + { 0x13040, 0x0 },
> + { 0x13140, 0x0 },
> + { 0x13240, 0x0 },
> + { 0x13340, 0x0 },
> + { 0x13440, 0x0 },
> + { 0x13540, 0x0 },
> + { 0x13640, 0x0 },
> + { 0x13740, 0x0 },
> + { 0x13840, 0x0 },
> + { 0x13030, 0x0 },
> + { 0x13130, 0x0 },
> + { 0x13230, 0x0 },
> + { 0x13330, 0x0 },
> + { 0x13430, 0x0 },
> + { 0x13530, 0x0 },
> + { 0x13630, 0x0 },
> + { 0x13730, 0x0 },
> + { 0x13830, 0x0 },
> +};
> +
> +/* P0 message block paremeter for training firmware */
> +static struct dram_cfg_param ddr_fsp0_cfg[] = {
> + { 0xd0000, 0x0 },
> + { 0x54003, 0xbb8 },
> + { 0x54004, 0x2 },
> + { 0x54005, 0x2228 },
> + { 0x54006, 0x11 },
> + { 0x54008, 0x131f },
> + { 0x54009, 0xc8 },
> + { 0x5400b, 0x2 },
> + { 0x54012, 0x310 },
> + { 0x54019, 0x2dd4 },
> + { 0x5401a, 0x31 },
> + { 0x5401b, 0x4d66 },
> + { 0x5401c, 0x4d00 },
> + { 0x5401e, 0x16 },
> + { 0x5401f, 0x2dd4 },
> + { 0x54020, 0x31 },
> + { 0x54021, 0x4d66 },
> + { 0x54022, 0x4d00 },
> + { 0x54024, 0x16 },
> + { 0x5402b, 0x1000 },
> + { 0x5402c, 0x3 },
> + { 0x54032, 0xd400 },
> + { 0x54033, 0x312d },
> + { 0x54034, 0x6600 },
> + { 0x54035, 0x4d },
> + { 0x54036, 0x4d },
> + { 0x54037, 0x1600 },
> + { 0x54038, 0xd400 },
> + { 0x54039, 0x312d },
> + { 0x5403a, 0x6600 },
> + { 0x5403b, 0x4d },
> + { 0x5403c, 0x4d },
> + { 0x5403d, 0x1600 },
> + { 0xd0000, 0x1 },
> +};
> +
> +/* P1 message block paremeter for training firmware */
> +static struct dram_cfg_param ddr_fsp1_cfg[] = {
> + { 0xd0000, 0x0 },
> + { 0x54002, 0x101 },
> + { 0x54003, 0x190 },
> + { 0x54004, 0x2 },
> + { 0x54005, 0x2228 },
> + { 0x54006, 0x11 },
> + { 0x54008, 0x121f },
> + { 0x54009, 0xc8 },
> + { 0x5400b, 0x2 },
> + { 0x54012, 0x310 },
> + { 0x54019, 0x84 },
> + { 0x5401a, 0x31 },
> + { 0x5401b, 0x4d66 },
> + { 0x5401c, 0x4d00 },
> + { 0x5401e, 0x16 },
> + { 0x5401f, 0x84 },
> + { 0x54020, 0x31 },
> + { 0x54021, 0x4d66 },
> + { 0x54022, 0x4d00 },
> + { 0x54024, 0x16 },
> + { 0x5402b, 0x1000 },
> + { 0x5402c, 0x3 },
> + { 0x54032, 0x8400 },
> + { 0x54033, 0x3100 },
> + { 0x54034, 0x6600 },
> + { 0x54035, 0x4d },
> + { 0x54036, 0x4d },
> + { 0x54037, 0x1600 },
> + { 0x54038, 0x8400 },
> + { 0x54039, 0x3100 },
> + { 0x5403a, 0x6600 },
> + { 0x5403b, 0x4d },
> + { 0x5403c, 0x4d },
> + { 0x5403d, 0x1600 },
> + { 0xd0000, 0x1 },
> +};
> +
> +/* P2 message block paremeter for training firmware */
> +static struct dram_cfg_param ddr_fsp2_cfg[] = {
> + { 0xd0000, 0x0 },
> + { 0x54002, 0x102 },
> + { 0x54003, 0x64 },
> + { 0x54004, 0x2 },
> + { 0x54005, 0x2228 },
> + { 0x54006, 0x11 },
> + { 0x54008, 0x121f },
> + { 0x54009, 0xc8 },
> + { 0x5400b, 0x2 },
> + { 0x54012, 0x310 },
> + { 0x54019, 0x84 },
> + { 0x5401a, 0x31 },
> + { 0x5401b, 0x4d66 },
> + { 0x5401c, 0x4d00 },
> + { 0x5401e, 0x16 },
> + { 0x5401f, 0x84 },
> + { 0x54020, 0x31 },
> + { 0x54021, 0x4d66 },
> + { 0x54022, 0x4d00 },
> + { 0x54024, 0x16 },
> + { 0x5402b, 0x1000 },
> + { 0x5402c, 0x3 },
> + { 0x54032, 0x8400 },
> + { 0x54033, 0x3100 },
> + { 0x54034, 0x6600 },
> + { 0x54035, 0x4d },
> + { 0x54036, 0x4d },
> + { 0x54037, 0x1600 },
> + { 0x54038, 0x8400 },
> + { 0x54039, 0x3100 },
> + { 0x5403a, 0x6600 },
> + { 0x5403b, 0x4d },
> + { 0x5403c, 0x4d },
> + { 0x5403d, 0x1600 },
> + { 0xd0000, 0x1 },
> +};
> +
> +/* P0 2D message block paremeter for training firmware */
> +static struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
> + { 0xd0000, 0x0 },
> + { 0x54003, 0xbb8 },
> + { 0x54004, 0x2 },
> + { 0x54005, 0x2228 },
> + { 0x54006, 0x11 },
> + { 0x54008, 0x61 },
> + { 0x54009, 0xc8 },
> + { 0x5400b, 0x2 },
> + { 0x5400d, 0x100 },
> + { 0x5400f, 0x100 },
> + { 0x54010, 0x1f7f },
> + { 0x54012, 0x310 },
> + { 0x54019, 0x2dd4 },
> + { 0x5401a, 0x31 },
> + { 0x5401b, 0x4d66 },
> + { 0x5401c, 0x4d00 },
> + { 0x5401e, 0x16 },
> + { 0x5401f, 0x2dd4 },
> + { 0x54020, 0x31 },
> + { 0x54021, 0x4d66 },
> + { 0x54022, 0x4d00 },
> + { 0x54024, 0x16 },
> + { 0x5402b, 0x1000 },
> + { 0x5402c, 0x3 },
> + { 0x54032, 0xd400 },
> + { 0x54033, 0x312d },
> + { 0x54034, 0x6600 },
> + { 0x54035, 0x4d },
> + { 0x54036, 0x4d },
> + { 0x54037, 0x1600 },
> + { 0x54038, 0xd400 },
> + { 0x54039, 0x312d },
> + { 0x5403a, 0x6600 },
> + { 0x5403b, 0x4d },
> + { 0x5403c, 0x4d },
> + { 0x5403d, 0x1600 },
> + { 0xd0000, 0x1 },
> +};
> +
> +/* DRAM PHY init engine image */
> +static struct dram_cfg_param ddr_phy_pie[] = {
> + { 0xd0000, 0x0 },
> + { 0x90000, 0x10 },
> + { 0x90001, 0x400 },
> + { 0x90002, 0x10e },
> + { 0x90003, 0x0 },
> + { 0x90004, 0x0 },
> + { 0x90005, 0x8 },
> + { 0x90029, 0xb },
> + { 0x9002a, 0x480 },
> + { 0x9002b, 0x109 },
> + { 0x9002c, 0x8 },
> + { 0x9002d, 0x448 },
> + { 0x9002e, 0x139 },
> + { 0x9002f, 0x8 },
> + { 0x90030, 0x478 },
> + { 0x90031, 0x109 },
> + { 0x90032, 0x0 },
> + { 0x90033, 0xe8 },
> + { 0x90034, 0x109 },
> + { 0x90035, 0x2 },
> + { 0x90036, 0x10 },
> + { 0x90037, 0x139 },
> + { 0x90038, 0xf },
> + { 0x90039, 0x7c0 },
> + { 0x9003a, 0x139 },
> + { 0x9003b, 0x44 },
> + { 0x9003c, 0x630 },
> + { 0x9003d, 0x159 },
> + { 0x9003e, 0x14f },
> + { 0x9003f, 0x630 },
> + { 0x90040, 0x159 },
> + { 0x90041, 0x47 },
> + { 0x90042, 0x630 },
> + { 0x90043, 0x149 },
> + { 0x90044, 0x4f },
> + { 0x90045, 0x630 },
> + { 0x90046, 0x179 },
> + { 0x90047, 0x8 },
> + { 0x90048, 0xe0 },
> + { 0x90049, 0x109 },
> + { 0x9004a, 0x0 },
> + { 0x9004b, 0x7c8 },
> + { 0x9004c, 0x109 },
> + { 0x9004d, 0x0 },
> + { 0x9004e, 0x1 },
> + { 0x9004f, 0x8 },
> + { 0x90050, 0x0 },
> + { 0x90051, 0x45a },
> + { 0x90052, 0x9 },
> + { 0x90053, 0x0 },
> + { 0x90054, 0x448 },
> + { 0x90055, 0x109 },
> + { 0x90056, 0x40 },
> + { 0x90057, 0x630 },
> + { 0x90058, 0x179 },
> + { 0x90059, 0x1 },
> + { 0x9005a, 0x618 },
> + { 0x9005b, 0x109 },
> + { 0x9005c, 0x40c0 },
> + { 0x9005d, 0x630 },
> + { 0x9005e, 0x149 },
> + { 0x9005f, 0x8 },
> + { 0x90060, 0x4 },
> + { 0x90061, 0x48 },
> + { 0x90062, 0x4040 },
> + { 0x90063, 0x630 },
> + { 0x90064, 0x149 },
> + { 0x90065, 0x0 },
> + { 0x90066, 0x4 },
> + { 0x90067, 0x48 },
> + { 0x90068, 0x40 },
> + { 0x90069, 0x630 },
> + { 0x9006a, 0x149 },
> + { 0x9006b, 0x10 },
> + { 0x9006c, 0x4 },
> + { 0x9006d, 0x18 },
> + { 0x9006e, 0x0 },
> + { 0x9006f, 0x4 },
> + { 0x90070, 0x78 },
> + { 0x90071, 0x549 },
> + { 0x90072, 0x630 },
> + { 0x90073, 0x159 },
> + { 0x90074, 0xd49 },
> + { 0x90075, 0x630 },
> + { 0x90076, 0x159 },
> + { 0x90077, 0x94a },
> + { 0x90078, 0x630 },
> + { 0x90079, 0x159 },
> + { 0x9007a, 0x441 },
> + { 0x9007b, 0x630 },
> + { 0x9007c, 0x149 },
> + { 0x9007d, 0x42 },
> + { 0x9007e, 0x630 },
> + { 0x9007f, 0x149 },
> + { 0x90080, 0x1 },
> + { 0x90081, 0x630 },
> + { 0x90082, 0x149 },
> + { 0x90083, 0x0 },
> + { 0x90084, 0xe0 },
> + { 0x90085, 0x109 },
> + { 0x90086, 0xa },
> + { 0x90087, 0x10 },
> + { 0x90088, 0x109 },
> + { 0x90089, 0x9 },
> + { 0x9008a, 0x3c0 },
> + { 0x9008b, 0x149 },
> + { 0x9008c, 0x9 },
> + { 0x9008d, 0x3c0 },
> + { 0x9008e, 0x159 },
> + { 0x9008f, 0x18 },
> + { 0x90090, 0x10 },
> + { 0x90091, 0x109 },
> + { 0x90092, 0x0 },
> + { 0x90093, 0x3c0 },
> + { 0x90094, 0x109 },
> + { 0x90095, 0x18 },
> + { 0x90096, 0x4 },
> + { 0x90097, 0x48 },
> + { 0x90098, 0x18 },
> + { 0x90099, 0x4 },
> + { 0x9009a, 0x58 },
> + { 0x9009b, 0xa },
> + { 0x9009c, 0x10 },
> + { 0x9009d, 0x109 },
> + { 0x9009e, 0x2 },
> + { 0x9009f, 0x10 },
> + { 0x900a0, 0x109 },
> + { 0x900a1, 0x5 },
> + { 0x900a2, 0x7c0 },
> + { 0x900a3, 0x109 },
> + { 0x900a4, 0x10 },
> + { 0x900a5, 0x10 },
> + { 0x900a6, 0x109 },
> + { 0x40000, 0x811 },
> + { 0x40020, 0x880 },
> + { 0x40040, 0x0 },
> + { 0x40060, 0x0 },
> + { 0x40001, 0x4008 },
> + { 0x40021, 0x83 },
> + { 0x40041, 0x4f },
> + { 0x40061, 0x0 },
> + { 0x40002, 0x4040 },
> + { 0x40022, 0x83 },
> + { 0x40042, 0x51 },
> + { 0x40062, 0x0 },
> + { 0x40003, 0x811 },
> + { 0x40023, 0x880 },
> + { 0x40043, 0x0 },
> + { 0x40063, 0x0 },
> + { 0x40004, 0x720 },
> + { 0x40024, 0xf },
> + { 0x40044, 0x1740 },
> + { 0x40064, 0x0 },
> + { 0x40005, 0x16 },
> + { 0x40025, 0x83 },
> + { 0x40045, 0x4b },
> + { 0x40065, 0x0 },
> + { 0x40006, 0x716 },
> + { 0x40026, 0xf },
> + { 0x40046, 0x2001 },
> + { 0x40066, 0x0 },
> + { 0x40007, 0x716 },
> + { 0x40027, 0xf },
> + { 0x40047, 0x2800 },
> + { 0x40067, 0x0 },
> + { 0x40008, 0x716 },
> + { 0x40028, 0xf },
> + { 0x40048, 0xf00 },
> + { 0x40068, 0x0 },
> + { 0x40009, 0x720 },
> + { 0x40029, 0xf },
> + { 0x40049, 0x1400 },
> + { 0x40069, 0x0 },
> + { 0x4000a, 0xe08 },
> + { 0x4002a, 0xc15 },
> + { 0x4004a, 0x0 },
> + { 0x4006a, 0x0 },
> + { 0x4000b, 0x623 },
> + { 0x4002b, 0x15 },
> + { 0x4004b, 0x0 },
> + { 0x4006b, 0x0 },
> + { 0x4000c, 0x4028 },
> + { 0x4002c, 0x80 },
> + { 0x4004c, 0x0 },
> + { 0x4006c, 0x0 },
> + { 0x4000d, 0xe08 },
> + { 0x4002d, 0xc1a },
> + { 0x4004d, 0x0 },
> + { 0x4006d, 0x0 },
> + { 0x4000e, 0x623 },
> + { 0x4002e, 0x1a },
> + { 0x4004e, 0x0 },
> + { 0x4006e, 0x0 },
> + { 0x4000f, 0x4040 },
> + { 0x4002f, 0x80 },
> + { 0x4004f, 0x0 },
> + { 0x4006f, 0x0 },
> + { 0x40010, 0x2604 },
> + { 0x40030, 0x15 },
> + { 0x40050, 0x0 },
> + { 0x40070, 0x0 },
> + { 0x40011, 0x708 },
> + { 0x40031, 0x5 },
> + { 0x40051, 0x0 },
> + { 0x40071, 0x2002 },
> + { 0x40012, 0x8 },
> + { 0x40032, 0x80 },
> + { 0x40052, 0x0 },
> + { 0x40072, 0x0 },
> + { 0x40013, 0x2604 },
> + { 0x40033, 0x1a },
> + { 0x40053, 0x0 },
> + { 0x40073, 0x0 },
> + { 0x40014, 0x708 },
> + { 0x40034, 0xa },
> + { 0x40054, 0x0 },
> + { 0x40074, 0x2002 },
> + { 0x40015, 0x4040 },
> + { 0x40035, 0x80 },
> + { 0x40055, 0x0 },
> + { 0x40075, 0x0 },
> + { 0x40016, 0x60a },
> + { 0x40036, 0x15 },
> + { 0x40056, 0x1200 },
> + { 0x40076, 0x0 },
> + { 0x40017, 0x61a },
> + { 0x40037, 0x15 },
> + { 0x40057, 0x1300 },
> + { 0x40077, 0x0 },
> + { 0x40018, 0x60a },
> + { 0x40038, 0x1a },
> + { 0x40058, 0x1200 },
> + { 0x40078, 0x0 },
> + { 0x40019, 0x642 },
> + { 0x40039, 0x1a },
> + { 0x40059, 0x1300 },
> + { 0x40079, 0x0 },
> + { 0x4001a, 0x4808 },
> + { 0x4003a, 0x880 },
> + { 0x4005a, 0x0 },
> + { 0x4007a, 0x0 },
> + { 0x900a7, 0x0 },
> + { 0x900a8, 0x790 },
> + { 0x900a9, 0x11a },
> + { 0x900aa, 0x8 },
> + { 0x900ab, 0x7aa },
> + { 0x900ac, 0x2a },
> + { 0x900ad, 0x10 },
> + { 0x900ae, 0x7b2 },
> + { 0x900af, 0x2a },
> + { 0x900b0, 0x0 },
> + { 0x900b1, 0x7c8 },
> + { 0x900b2, 0x109 },
> + { 0x900b3, 0x10 },
> + { 0x900b4, 0x2a8 },
> + { 0x900b5, 0x129 },
> + { 0x900b6, 0x8 },
> + { 0x900b7, 0x370 },
> + { 0x900b8, 0x129 },
> + { 0x900b9, 0xa },
> + { 0x900ba, 0x3c8 },
> + { 0x900bb, 0x1a9 },
> + { 0x900bc, 0xc },
> + { 0x900bd, 0x408 },
> + { 0x900be, 0x199 },
> + { 0x900bf, 0x14 },
> + { 0x900c0, 0x790 },
> + { 0x900c1, 0x11a },
> + { 0x900c2, 0x8 },
> + { 0x900c3, 0x4 },
> + { 0x900c4, 0x18 },
> + { 0x900c5, 0xe },
> + { 0x900c6, 0x408 },
> + { 0x900c7, 0x199 },
> + { 0x900c8, 0x8 },
> + { 0x900c9, 0x8568 },
> + { 0x900ca, 0x108 },
> + { 0x900cb, 0x18 },
> + { 0x900cc, 0x790 },
> + { 0x900cd, 0x16a },
> + { 0x900ce, 0x8 },
> + { 0x900cf, 0x1d8 },
> + { 0x900d0, 0x169 },
> + { 0x900d1, 0x10 },
> + { 0x900d2, 0x8558 },
> + { 0x900d3, 0x168 },
> + { 0x900d4, 0x70 },
> + { 0x900d5, 0x788 },
> + { 0x900d6, 0x16a },
> + { 0x900d7, 0x1ff8 },
> + { 0x900d8, 0x85a8 },
> + { 0x900d9, 0x1e8 },
> + { 0x900da, 0x50 },
> + { 0x900db, 0x798 },
> + { 0x900dc, 0x16a },
> + { 0x900dd, 0x60 },
> + { 0x900de, 0x7a0 },
> + { 0x900df, 0x16a },
> + { 0x900e0, 0x8 },
> + { 0x900e1, 0x8310 },
> + { 0x900e2, 0x168 },
> + { 0x900e3, 0x8 },
> + { 0x900e4, 0xa310 },
> + { 0x900e5, 0x168 },
> + { 0x900e6, 0xa },
> + { 0x900e7, 0x408 },
> + { 0x900e8, 0x169 },
> + { 0x900e9, 0x6e },
> + { 0x900ea, 0x0 },
> + { 0x900eb, 0x68 },
> + { 0x900ec, 0x0 },
> + { 0x900ed, 0x408 },
> + { 0x900ee, 0x169 },
> + { 0x900ef, 0x0 },
> + { 0x900f0, 0x8310 },
> + { 0x900f1, 0x168 },
> + { 0x900f2, 0x0 },
> + { 0x900f3, 0xa310 },
> + { 0x900f4, 0x168 },
> + { 0x900f5, 0x1ff8 },
> + { 0x900f6, 0x85a8 },
> + { 0x900f7, 0x1e8 },
> + { 0x900f8, 0x68 },
> + { 0x900f9, 0x798 },
> + { 0x900fa, 0x16a },
> + { 0x900fb, 0x78 },
> + { 0x900fc, 0x7a0 },
> + { 0x900fd, 0x16a },
> + { 0x900fe, 0x68 },
> + { 0x900ff, 0x790 },
> + { 0x90100, 0x16a },
> + { 0x90101, 0x8 },
> + { 0x90102, 0x8b10 },
> + { 0x90103, 0x168 },
> + { 0x90104, 0x8 },
> + { 0x90105, 0xab10 },
> + { 0x90106, 0x168 },
> + { 0x90107, 0xa },
> + { 0x90108, 0x408 },
> + { 0x90109, 0x169 },
> + { 0x9010a, 0x58 },
> + { 0x9010b, 0x0 },
> + { 0x9010c, 0x68 },
> + { 0x9010d, 0x0 },
> + { 0x9010e, 0x408 },
> + { 0x9010f, 0x169 },
> + { 0x90110, 0x0 },
> + { 0x90111, 0x8b10 },
> + { 0x90112, 0x168 },
> + { 0x90113, 0x0 },
> + { 0x90114, 0xab10 },
> + { 0x90115, 0x168 },
> + { 0x90116, 0x0 },
> + { 0x90117, 0x1d8 },
> + { 0x90118, 0x169 },
> + { 0x90119, 0x80 },
> + { 0x9011a, 0x790 },
> + { 0x9011b, 0x16a },
> + { 0x9011c, 0x18 },
> + { 0x9011d, 0x7aa },
> + { 0x9011e, 0x6a },
> + { 0x9011f, 0xa },
> + { 0x90120, 0x0 },
> + { 0x90121, 0x1e9 },
> + { 0x90122, 0x8 },
> + { 0x90123, 0x8080 },
> + { 0x90124, 0x108 },
> + { 0x90125, 0xf },
> + { 0x90126, 0x408 },
> + { 0x90127, 0x169 },
> + { 0x90128, 0xc },
> + { 0x90129, 0x0 },
> + { 0x9012a, 0x68 },
> + { 0x9012b, 0x9 },
> + { 0x9012c, 0x0 },
> + { 0x9012d, 0x1a9 },
> + { 0x9012e, 0x0 },
> + { 0x9012f, 0x408 },
> + { 0x90130, 0x169 },
> + { 0x90131, 0x0 },
> + { 0x90132, 0x8080 },
> + { 0x90133, 0x108 },
> + { 0x90134, 0x8 },
> + { 0x90135, 0x7aa },
> + { 0x90136, 0x6a },
> + { 0x90137, 0x0 },
> + { 0x90138, 0x8568 },
> + { 0x90139, 0x108 },
> + { 0x9013a, 0xb7 },
> + { 0x9013b, 0x790 },
> + { 0x9013c, 0x16a },
> + { 0x9013d, 0x1f },
> + { 0x9013e, 0x0 },
> + { 0x9013f, 0x68 },
> + { 0x90140, 0x8 },
> + { 0x90141, 0x8558 },
> + { 0x90142, 0x168 },
> + { 0x90143, 0xf },
> + { 0x90144, 0x408 },
> + { 0x90145, 0x169 },
> + { 0x90146, 0xc },
> + { 0x90147, 0x0 },
> + { 0x90148, 0x68 },
> + { 0x90149, 0x0 },
> + { 0x9014a, 0x408 },
> + { 0x9014b, 0x169 },
> + { 0x9014c, 0x0 },
> + { 0x9014d, 0x8558 },
> + { 0x9014e, 0x168 },
> + { 0x9014f, 0x8 },
> + { 0x90150, 0x3c8 },
> + { 0x90151, 0x1a9 },
> + { 0x90152, 0x3 },
> + { 0x90153, 0x370 },
> + { 0x90154, 0x129 },
> + { 0x90155, 0x20 },
> + { 0x90156, 0x2aa },
> + { 0x90157, 0x9 },
> + { 0x90158, 0x0 },
> + { 0x90159, 0x400 },
> + { 0x9015a, 0x10e },
> + { 0x9015b, 0x8 },
> + { 0x9015c, 0xe8 },
> + { 0x9015d, 0x109 },
> + { 0x9015e, 0x0 },
> + { 0x9015f, 0x8140 },
> + { 0x90160, 0x10c },
> + { 0x90161, 0x10 },
> + { 0x90162, 0x8138 },
> + { 0x90163, 0x10c },
> + { 0x90164, 0x8 },
> + { 0x90165, 0x7c8 },
> + { 0x90166, 0x101 },
> + { 0x90167, 0x8 },
> + { 0x90168, 0x0 },
> + { 0x90169, 0x8 },
> + { 0x9016a, 0x8 },
> + { 0x9016b, 0x448 },
> + { 0x9016c, 0x109 },
> + { 0x9016d, 0xf },
> + { 0x9016e, 0x7c0 },
> + { 0x9016f, 0x109 },
> + { 0x90170, 0x0 },
> + { 0x90171, 0xe8 },
> + { 0x90172, 0x109 },
> + { 0x90173, 0x47 },
> + { 0x90174, 0x630 },
> + { 0x90175, 0x109 },
> + { 0x90176, 0x8 },
> + { 0x90177, 0x618 },
> + { 0x90178, 0x109 },
> + { 0x90179, 0x8 },
> + { 0x9017a, 0xe0 },
> + { 0x9017b, 0x109 },
> + { 0x9017c, 0x0 },
> + { 0x9017d, 0x7c8 },
> + { 0x9017e, 0x109 },
> + { 0x9017f, 0x8 },
> + { 0x90180, 0x8140 },
> + { 0x90181, 0x10c },
> + { 0x90182, 0x0 },
> + { 0x90183, 0x1 },
> + { 0x90184, 0x8 },
> + { 0x90185, 0x8 },
> + { 0x90186, 0x4 },
> + { 0x90187, 0x8 },
> + { 0x90188, 0x8 },
> + { 0x90189, 0x7c8 },
> + { 0x9018a, 0x101 },
> + { 0x90006, 0x0 },
> + { 0x90007, 0x0 },
> + { 0x90008, 0x8 },
> + { 0x90009, 0x0 },
> + { 0x9000a, 0x0 },
> + { 0x9000b, 0x0 },
> + { 0xd00e7, 0x400 },
> + { 0x90017, 0x0 },
> + { 0x9001f, 0x2a },
> + { 0x90026, 0x6a },
> + { 0x400d0, 0x0 },
> + { 0x400d1, 0x101 },
> + { 0x400d2, 0x105 },
> + { 0x400d3, 0x107 },
> + { 0x400d4, 0x10f },
> + { 0x400d5, 0x202 },
> + { 0x400d6, 0x20a },
> + { 0x400d7, 0x20b },
> + { 0x2003a, 0x2 },
> + { 0x2000b, 0x5d },
> + { 0x2000c, 0xbb },
> + { 0x2000d, 0x753 },
> + { 0x2000e, 0x2c },
> + { 0x12000b, 0xc },
> + { 0x12000c, 0x19 },
> + { 0x12000d, 0xfa },
> + { 0x12000e, 0x10 },
> + { 0x22000b, 0x3 },
> + { 0x22000c, 0x6 },
> + { 0x22000d, 0x3e },
> + { 0x22000e, 0x10 },
> + { 0x9000c, 0x0 },
> + { 0x9000d, 0x173 },
> + { 0x9000e, 0x60 },
> + { 0x9000f, 0x6110 },
> + { 0x90010, 0x2152 },
> + { 0x90011, 0xdfbd },
> + { 0x90012, 0x60 },
> + { 0x90013, 0x6152 },
> + { 0x20010, 0x5a },
> + { 0x20011, 0x3 },
> + { 0x40080, 0xe0 },
> + { 0x40081, 0x12 },
> + { 0x40082, 0xe0 },
> + { 0x40083, 0x12 },
> + { 0x40084, 0xe0 },
> + { 0x40085, 0x12 },
> + { 0x140080, 0xe0 },
> + { 0x140081, 0x12 },
> + { 0x140082, 0xe0 },
> + { 0x140083, 0x12 },
> + { 0x140084, 0xe0 },
> + { 0x140085, 0x12 },
> + { 0x240080, 0xe0 },
> + { 0x240081, 0x12 },
> + { 0x240082, 0xe0 },
> + { 0x240083, 0x12 },
> + { 0x240084, 0xe0 },
> + { 0x240085, 0x12 },
> + { 0x400fd, 0xf },
> + { 0x10011, 0x1 },
> + { 0x10012, 0x1 },
> + { 0x10013, 0x180 },
> + { 0x10018, 0x1 },
> + { 0x10002, 0x6209 },
> + { 0x100b2, 0x1 },
> + { 0x101b4, 0x1 },
> + { 0x102b4, 0x1 },
> + { 0x103b4, 0x1 },
> + { 0x104b4, 0x1 },
> + { 0x105b4, 0x1 },
> + { 0x106b4, 0x1 },
> + { 0x107b4, 0x1 },
> + { 0x108b4, 0x1 },
> + { 0x11011, 0x1 },
> + { 0x11012, 0x1 },
> + { 0x11013, 0x180 },
> + { 0x11018, 0x1 },
> + { 0x11002, 0x6209 },
> + { 0x110b2, 0x1 },
> + { 0x111b4, 0x1 },
> + { 0x112b4, 0x1 },
> + { 0x113b4, 0x1 },
> + { 0x114b4, 0x1 },
> + { 0x115b4, 0x1 },
> + { 0x116b4, 0x1 },
> + { 0x117b4, 0x1 },
> + { 0x118b4, 0x1 },
> + { 0x12011, 0x1 },
> + { 0x12012, 0x1 },
> + { 0x12013, 0x180 },
> + { 0x12018, 0x1 },
> + { 0x12002, 0x6209 },
> + { 0x120b2, 0x1 },
> + { 0x121b4, 0x1 },
> + { 0x122b4, 0x1 },
> + { 0x123b4, 0x1 },
> + { 0x124b4, 0x1 },
> + { 0x125b4, 0x1 },
> + { 0x126b4, 0x1 },
> + { 0x127b4, 0x1 },
> + { 0x128b4, 0x1 },
> + { 0x13011, 0x1 },
> + { 0x13012, 0x1 },
> + { 0x13013, 0x180 },
> + { 0x13018, 0x1 },
> + { 0x13002, 0x6209 },
> + { 0x130b2, 0x1 },
> + { 0x131b4, 0x1 },
> + { 0x132b4, 0x1 },
> + { 0x133b4, 0x1 },
> + { 0x134b4, 0x1 },
> + { 0x135b4, 0x1 },
> + { 0x136b4, 0x1 },
> + { 0x137b4, 0x1 },
> + { 0x138b4, 0x1 },
> + { 0x2003a, 0x2 },
> + { 0xc0080, 0x2 },
> + { 0xd0000, 0x1 }
> +};
> +
> +static struct dram_fsp_msg ddr_dram_fsp_msg[] = {
> + {
> + /* P0 3000mts 1D */
> + .drate = 3000,
> + .fw_type = FW_1D_IMAGE,
> + .fsp_cfg = ddr_fsp0_cfg,
> + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
> + },
> + {
> + /* P1 400mts 1D */
> + .drate = 400,
> + .fw_type = FW_1D_IMAGE,
> + .fsp_cfg = ddr_fsp1_cfg,
> + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
> + },
> + {
> + /* P2 100mts 1D */
> + .drate = 100,
> + .fw_type = FW_1D_IMAGE,
> + .fsp_cfg = ddr_fsp2_cfg,
> + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
> + },
> + {
> + /* P0 3000mts 2D */
> + .drate = 3000,
> + .fw_type = FW_2D_IMAGE,
> + .fsp_cfg = ddr_fsp0_2d_cfg,
> + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
> + },
> +};
> +
> +/* ddr timing config params */
> +struct dram_timing_info dmo_imx8mm_sbc_dram_timing_32_32 = {
> + .ddrc_cfg = ddr_ddrc_cfg,
> + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
> + .ddrphy_cfg = ddr_ddrphy_cfg,
> + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
> + .fsp_msg = ddr_dram_fsp_msg,
> + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
> + .ddrphy_trained_csr = ddr_ddrphy_trained_csr,
> + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
> + .ddrphy_pie = ddr_phy_pie,
> + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
> + .fsp_table = { 3000, 400, 100, },
> +};
> diff --git a/board/data_modul/imx8mm_edm_sbc/spl.c b/board/data_modul/imx8mm_edm_sbc/spl.c
> new file mode 100644
> index 00000000000..36cad14fc41
> --- /dev/null
> +++ b/board/data_modul/imx8mm_edm_sbc/spl.c
> @@ -0,0 +1,179 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2022 Marek Vasut <marex at denx.de>
> + */
> +
> +#include <common.h>
> +#include <hang.h>
> +#include <image.h>
> +#include <init.h>
> +#include <spl.h>
> +#include <asm/io.h>
> +#include <asm-generic/gpio.h>
> +#include <asm/arch/clock.h>
> +#include <asm/arch/imx8mm_pins.h>
> +#include <asm/arch/sys_proto.h>
> +#include <asm/arch/ddr.h>
> +#include <asm/mach-imx/boot_mode.h>
> +
> +#include <dm/uclass.h>
> +#include <dm/device.h>
> +#include <dm/uclass-internal.h>
> +#include <dm/device-internal.h>
> +
> +#include <power/pmic.h>
> +#include <power/bd71837.h>
> +
> +#include "lpddr4_timing.h"
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
> +#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
> +
> +static const iomux_v3_cfg_t uart_pads[] = {
> + IMX8MM_PAD_UART3_RXD_UART3_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
> + IMX8MM_PAD_UART3_TXD_UART3_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
> +};
> +
> +static const iomux_v3_cfg_t wdog_pads[] = {
> + IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
> +};
> +
> +static void data_modul_imx8mm_edm_sbc_early_init_f(void)
> +{
> + struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
> +
> + imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
> +
> + set_wdog_reset(wdog);
> +
> + imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
> +}
> +
> +static int data_modul_imx8mm_edm_sbc_board_power_init(void)
> +{
> + struct udevice *dev;
> + int ret;
> +
> + ret = pmic_get("pmic at 4b", &dev);
> + if (ret == -ENODEV) {
> + puts("Failed to get PMIC\n");
> + return 0;
> + }
> + if (ret != 0)
> + return ret;
> +
> + /* Unlock the PMIC regs */
> + pmic_reg_write(dev, BD718XX_REGLOCK, 0x1);
> +
> + /* Increase VDD_SOC to typical value 0.85V before first DRAM access */
> + pmic_reg_write(dev, BD718XX_BUCK1_VOLT_RUN, 0x0f);
> +
> + /* Increase VDD_DRAM to 0.975V for 3GHz DDR */
> + pmic_reg_write(dev, BD718XX_1ST_NODVS_BUCK_VOLT, 0x83);
> +
> + /* Lock the PMIC regs */
> + pmic_reg_write(dev, BD718XX_REGLOCK, 0x11);
> +
> + return 0;
> +}
> +
> +int spl_board_boot_device(enum boot_device boot_dev_spl)
> +{
> + if (boot_dev_spl == MMC3_BOOT)
> + return BOOT_DEVICE_MMC2; /* eMMC */
> + else
> + return BOOT_DEVICE_MMC1; /* SD */
> +}
> +
> +void board_boot_order(u32 *spl_boot_list)
> +{
> + int boot_device = spl_boot_device();
> +
> + spl_boot_list[0] = boot_device; /* 1:SD 2:eMMC */
> +
> + if (boot_device == BOOT_DEVICE_MMC1)
> + spl_boot_list[1] = BOOT_DEVICE_MMC2; /* eMMC */
> + else
> + spl_boot_list[1] = BOOT_DEVICE_MMC1; /* SD */
> +
> + spl_boot_list[2] = BOOT_DEVICE_UART; /* YModem */
> + spl_boot_list[3] = BOOT_DEVICE_NONE;
> +}
> +
> +static struct dram_timing_info *dram_timing_info[8] = {
> + &dmo_imx8mm_sbc_dram_timing_32_32, /* 32 Gbit x32 */
> + NULL, /* 32 Gbit x16 */
> + &dmo_imx8mm_sbc_dram_timing_16_32, /* 16 Gbit x32 */
> + NULL, /* 16 Gbit x16 */
> + NULL, /* 8 Gbit x32 */
> + NULL, /* 8 Gbit x16 */
> + NULL, /* INVALID */
> + NULL, /* INVALID */
> +};
> +
> +static void spl_dram_init(void)
> +{
> + u8 memcfg = dmo_get_memcfg();
> + int i;
> +
> + printf("DDR: %d GiB x%d [0x%x]\n",
> + /* 0..4 GiB, 1..2 GiB, 0..1 GiB */
> + 4 >> ((memcfg >> 1) & 0x3),
> + /* 0..x32, 1..x16 */
> + 32 >> (memcfg & BIT(0)),
> + memcfg);
> +
> + if (!dram_timing_info[memcfg]) {
> + printf("Unsupported DRAM strapping, trying lowest supported. MEMCFG=0x%x\n",
> + memcfg);
> + for (i = ARRAY_SIZE(dram_timing_info) - 1; i >= 0; i--)
> + if (dram_timing_info[i]) /* Configuration found */
> + break;
> + }
> +
> + ddr_init(dram_timing_info[memcfg]);
> +}
> +
> +void board_init_f(ulong dummy)
> +{
> + struct udevice *dev;
> + int ret;
> +
> + icache_enable();
> +
> + arch_cpu_init();
> +
> + init_uart_clk(2);
> +
> + data_modul_imx8mm_edm_sbc_early_init_f();
> +
> + preloader_console_init();
> +
> + /* Clear the BSS. */
> + memset(__bss_start, 0, __bss_end - __bss_start);
> +
> + ret = spl_early_init();
> + if (ret) {
> + debug("spl_early_init() failed: %d\n", ret);
> + hang();
> + }
> +
> + ret = uclass_get_device_by_name(UCLASS_CLK,
> + "clock-controller at 30380000",
> + &dev);
> + if (ret < 0) {
> + printf("Failed to find clock node. Check device tree\n");
> + hang();
> + }
> +
> + enable_tzc380();
> +
> + data_modul_imx8mm_edm_sbc_board_power_init();
> +
> + /* DDR initialization */
> + spl_dram_init();
> +
> + board_init_r(NULL, 0);
> +}
> diff --git a/configs/imx8mm_data_modul_edm_sbc_defconfig b/configs/imx8mm_data_modul_edm_sbc_defconfig
> new file mode 100644
> index 00000000000..7a1164d251b
> --- /dev/null
> +++ b/configs/imx8mm_data_modul_edm_sbc_defconfig
> @@ -0,0 +1,229 @@
> +CONFIG_ARM=y
> +CONFIG_ARCH_IMX8M=y
> +CONFIG_SYS_TEXT_BASE=0x40200000
> +CONFIG_SYS_MALLOC_LEN=0x1000000
> +CONFIG_SYS_MALLOC_F_LEN=0x10000
> +CONFIG_SPL_GPIO=y
> +CONFIG_SPL_LIBCOMMON_SUPPORT=y
> +CONFIG_SPL_LIBGENERIC_SUPPORT=y
> +CONFIG_NR_DRAM_BANKS=1
> +CONFIG_ENV_SIZE=0x40000
> +CONFIG_ENV_OFFSET=0xFFFC0000
> +CONFIG_IMX_CONFIG="board/data_modul/imx8mm_edm_sbc/imximage.cfg"
> +CONFIG_DM_GPIO=y
> +CONFIG_DEFAULT_DEVICE_TREE="imx8mm-data-modul-edm-sbc"
> +CONFIG_SPL_TEXT_BASE=0x7E1000
> +CONFIG_TARGET_IMX8MM_DATA_MODUL_EDM_SBC=y
> +CONFIG_SPL_MMC=y
> +CONFIG_SPL_SERIAL=y
> +CONFIG_SPL_DRIVERS_MISC=y
> +CONFIG_BOOTCOUNT_BOOTLIMIT=3
> +CONFIG_SYS_BOOTCOUNT_ADDR=0x30370090
> +CONFIG_SPL=y
> +CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y
> +CONFIG_ENV_OFFSET_REDUND=0xFFFC0000
> +CONFIG_IMX_BOOTAUX=y
> +CONFIG_ENV_VARS_UBOOT_CONFIG=y
> +CONFIG_SYS_LOAD_ADDR=0x60000000
> +CONFIG_FIT=y
> +CONFIG_FIT_EXTERNAL_OFFSET=0x3000
> +CONFIG_SPL_LOAD_FIT=y
> +CONFIG_SPL_LOAD_FIT_ADDRESS=0x44000000
> +# CONFIG_USE_SPL_FIT_GENERATOR is not set
> +CONFIG_SUPPORT_RAW_INITRD=y
> +CONFIG_OF_SYSTEM_SETUP=y
> +CONFIG_USE_BOOTARGS=y
> +CONFIG_USE_BOOTCOMMAND=y
> +CONFIG_BOOTCOMMAND="run dmo_update_env ; load ${devtype} ${devnum}:${devpart} ${loadaddr} boot/fitImage && source ${loadaddr}:bootscr-boot.cmd ; reset"
> +CONFIG_USE_PREBOOT=y
> +CONFIG_PREBOOT="run dmo_preboot"
> +CONFIG_DEFAULT_FDT_FILE="imx8mm-data-modul-edm-sbc.dtb"
> +CONFIG_CONSOLE_MUX=y
> +CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
> +CONFIG_ARCH_MISC_INIT=y
> +CONFIG_BOARD_LATE_INIT=y
> +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
> +CONFIG_SPL_LEGACY_IMAGE_SUPPORT=y
> +CONFIG_SPL_LEGACY_IMAGE_CRC_CHECK=y
> +CONFIG_SPL_SEPARATE_BSS=y
> +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
> +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
> +CONFIG_SPL_I2C=y
> +CONFIG_SPL_POWER=y
> +CONFIG_SPL_RAM_SUPPORT=y
> +CONFIG_SPL_RAM_DEVICE=y
> +CONFIG_SPL_WATCHDOG=y
> +CONFIG_SPL_YMODEM_SUPPORT=y
> +CONFIG_HUSH_PARSER=y
> +CONFIG_SYS_PROMPT="u-boot=> "
> +# CONFIG_BOOTM_NETBSD is not set
> +# CONFIG_BOOTM_PLAN9 is not set
> +# CONFIG_BOOTM_RTEMS is not set
> +# CONFIG_BOOTM_VXWORKS is not set
> +CONFIG_CMD_ASKENV=y
> +# CONFIG_CMD_EXPORTENV is not set
> +CONFIG_CMD_ERASEENV=y
> +CONFIG_CRC32_VERIFY=y
> +CONFIG_CMD_EEPROM=y
> +CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
> +CONFIG_SYS_EEPROM_SIZE=16384
> +CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=6
> +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=20
> +CONFIG_CMD_MD5SUM=y
> +CONFIG_MD5SUM_VERIFY=y
> +CONFIG_CMD_MEMTEST=y
> +CONFIG_CMD_SHA1SUM=y
> +CONFIG_SHA1SUM_VERIFY=y
> +CONFIG_CMD_CLK=y
> +CONFIG_CMD_DFU=y
> +CONFIG_CMD_FUSE=y
> +CONFIG_CMD_GPIO=y
> +CONFIG_CMD_GPT=y
> +CONFIG_CMD_GPT_RENAME=y
> +CONFIG_CMD_I2C=y
> +CONFIG_CMD_LSBLK=y
> +CONFIG_CMD_MBR=y
> +CONFIG_CMD_MMC=y
> +CONFIG_CMD_BKOPS_ENABLE=y
> +CONFIG_CMD_MTD=y
> +CONFIG_CMD_PART=y
> +CONFIG_CMD_READ=y
> +CONFIG_CMD_SPI=y
> +CONFIG_CMD_USB=y
> +CONFIG_CMD_USB_SDP=y
> +CONFIG_CMD_USB_MASS_STORAGE=y
> +CONFIG_CMD_DHCP=y
> +CONFIG_CMD_MII=y
> +CONFIG_CMD_PING=y
> +CONFIG_CMD_PXE=y
> +CONFIG_CMD_BOOTCOUNT=y
> +CONFIG_CMD_CACHE=y
> +CONFIG_CMD_TIME=y
> +CONFIG_CMD_GETTIME=y
> +CONFIG_CMD_SYSBOOT=y
> +CONFIG_CMD_UUID=y
> +CONFIG_CMD_PMIC=y
> +CONFIG_CMD_REGULATOR=y
> +CONFIG_CMD_HASH=y
> +CONFIG_CMD_SMC=y
> +CONFIG_HASH_VERIFY=y
> +CONFIG_CMD_BTRFS=y
> +CONFIG_CMD_EXT2=y
> +CONFIG_CMD_EXT4=y
> +CONFIG_CMD_EXT4_WRITE=y
> +CONFIG_CMD_FAT=y
> +CONFIG_CMD_FS_GENERIC=y
> +CONFIG_CMD_FS_UUID=y
> +CONFIG_CMD_MTDPARTS=y
> +CONFIG_CMD_MTDPARTS_SHOW_NET_SIZES=y
> +CONFIG_MTDIDS_DEFAULT="nor0=flash at 0"
> +CONFIG_MTDPARTS_DEFAULT="mtdparts=flash at 0:-(sf)"
> +CONFIG_MMC_SPEED_MODE_SET=y
> +CONFIG_PARTITION_TYPE_GUID=y
> +CONFIG_OF_CONTROL=y
> +CONFIG_SPL_OF_CONTROL=y
> +CONFIG_ENV_OVERWRITE=y
> +CONFIG_ENV_IS_IN_MMC=y
> +CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
> +CONFIG_SYS_RELOC_GD_ENV_ADDR=y
> +CONFIG_SYS_MMC_ENV_PART=1
> +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
> +CONFIG_VERSION_VARIABLE=y
> +CONFIG_NET_RANDOM_ETHADDR=y
> +CONFIG_NETCONSOLE=y
> +CONFIG_IP_DEFRAG=y
> +CONFIG_TFTP_TSIZE=y
> +CONFIG_SPL_DM=y
> +CONFIG_REGMAP=y
> +CONFIG_SYSCON=y
> +CONFIG_BOOTCOUNT_LIMIT=y
> +CONFIG_SYS_BOOTCOUNT_MAGIC=0xB0C40000
> +CONFIG_SPL_CLK_COMPOSITE_CCF=y
> +CONFIG_CLK_COMPOSITE_CCF=y
> +CONFIG_SPL_CLK_IMX8MM=y
> +CONFIG_CLK_IMX8MM=y
> +CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000
> +CONFIG_DFU_TFTP=y
> +CONFIG_DFU_TIMEOUT=y
> +CONFIG_DFU_MMC=y
> +CONFIG_DFU_MTD=y
> +CONFIG_DFU_RAM=y
> +CONFIG_USB_FUNCTION_FASTBOOT=y
> +CONFIG_FASTBOOT_BUF_ADDR=0x42800000
> +CONFIG_FASTBOOT_BUF_SIZE=0x20000000
> +CONFIG_FASTBOOT_FLASH=y
> +CONFIG_FASTBOOT_FLASH_MMC_DEV=0
> +CONFIG_GPIO_HOG=y
> +CONFIG_MXC_GPIO=y
> +CONFIG_DM_I2C=y
> +# CONFIG_INPUT is not set
> +CONFIG_MISC=y
> +CONFIG_I2C_EEPROM=y
> +CONFIG_SYS_I2C_EEPROM_ADDR=0x50
> +CONFIG_SUPPORT_EMMC_BOOT=y
> +CONFIG_MMC_IO_VOLTAGE=y
> +CONFIG_SPL_MMC_IO_VOLTAGE=y
> +CONFIG_MMC_UHS_SUPPORT=y
> +# CONFIG_SPL_MMC_UHS_SUPPORT is not set
> +CONFIG_MMC_HS400_ES_SUPPORT=y
> +CONFIG_MMC_HS400_SUPPORT=y
> +CONFIG_FSL_USDHC=y
> +CONFIG_MTD=y
> +CONFIG_DM_MTD=y
> +CONFIG_DM_SPI_FLASH=y
> +CONFIG_SF_DEFAULT_SPEED=50000000
> +CONFIG_SPI_FLASH_SFDP_SUPPORT=y
> +# CONFIG_SPI_FLASH_UNLOCK_ALL is not set
> +CONFIG_SPI_FLASH_WINBOND=y
> +CONFIG_SPI_FLASH_MTD=y
> +CONFIG_PHYLIB=y
> +CONFIG_PHY_ATHEROS=y
> +CONFIG_DM_ETH=y
> +CONFIG_DM_MDIO=y
> +CONFIG_DM_ETH_PHY=y
> +CONFIG_FEC_MXC=y
> +CONFIG_RGMII=y
> +CONFIG_MII=y
> +CONFIG_PINCTRL=y
> +CONFIG_SPL_PINCTRL=y
> +CONFIG_PINCTRL_IMX8M=y
> +CONFIG_POWER_DOMAIN=y
> +CONFIG_IMX8M_POWER_DOMAIN=y
> +CONFIG_DM_PMIC=y
> +CONFIG_DM_PMIC_BD71837=y
> +CONFIG_SPL_DM_PMIC_BD71837=y
> +CONFIG_DM_REGULATOR=y
> +CONFIG_SPL_DM_REGULATOR=y
> +CONFIG_DM_REGULATOR_BD71837=y
> +CONFIG_SPL_DM_REGULATOR_BD71837=y
> +CONFIG_DM_REGULATOR_FIXED=y
> +CONFIG_DM_REGULATOR_GPIO=y
> +CONFIG_DM_RESET=y
> +CONFIG_DM_RTC=y
> +CONFIG_RTC_M41T62=y
> +CONFIG_CONS_INDEX=2
> +CONFIG_DM_SERIAL=y
> +# CONFIG_SPL_DM_SERIAL is not set
> +CONFIG_MXC_UART=y
> +CONFIG_SPI=y
> +CONFIG_DM_SPI=y
> +CONFIG_MXC_SPI=y
> +CONFIG_SYSRESET=y
> +CONFIG_SPL_SYSRESET=y
> +CONFIG_SYSRESET_PSCI=y
> +CONFIG_SYSRESET_WATCHDOG=y
> +CONFIG_DM_THERMAL=y
> +CONFIG_IMX_TMU=y
> +CONFIG_USB=y
> +# CONFIG_SPL_DM_USB is not set
> +CONFIG_USB_EHCI_HCD=y
> +CONFIG_USB_STORAGE=y
> +CONFIG_USB_GADGET=y
> +CONFIG_USB_GADGET_MANUFACTURER="Data Modul"
> +CONFIG_USB_GADGET_VENDOR_NUM=0x0525
> +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
> +CONFIG_CI_UDC=y
> +CONFIG_SDP_LOADADDR=0x0
> +CONFIG_USB_FUNCTION_ACM=y
> +CONFIG_IMX_WATCHDOG=y
> +CONFIG_OF_LIBFDT_OVERLAY=y
> diff --git a/include/configs/imx8mm_data_modul_edm_sbc.h b/include/configs/imx8mm_data_modul_edm_sbc.h
> new file mode 100644
> index 00000000000..3772026816f
> --- /dev/null
> +++ b/include/configs/imx8mm_data_modul_edm_sbc.h
> @@ -0,0 +1,133 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright 2022 Marek Vasut <marex at denx.de>
> + */
> +
> +#ifndef __IMX8MM_DATA_MODUL_EDM_SBC_H
> +#define __IMX8MM_DATA_MODUL_EDM_SBC_H
> +
> +#include <linux/sizes.h>
> +#include <linux/stringify.h>
> +#include <asm/arch/imx-regs.h>
> +
> +#define CONFIG_SYS_BOOTM_LEN SZ_128M
> +
> +#define CONFIG_SPL_MAX_SIZE (148 * 1024)
> +#define CONFIG_SYS_MONITOR_LEN SZ_1M
> +
> +#define CONFIG_SPL_STACK 0x920000
> +#ifdef CONFIG_SPL_BUILD
> +#define CONFIG_SPL_BSS_START_ADDR 0x910000
> +#define CONFIG_SPL_BSS_MAX_SIZE SZ_8K /* 8 kiB */
> +#define CONFIG_SYS_SPL_MALLOC_START 0x42200000
> +#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_16M /* 16 MiB */
> +
> +#define CONFIG_MALLOC_F_ADDR 0x930000
> +
> +/* For RAW image gives a error info not panic */
> +#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
> +
> +#endif
> +
> +/* Link Definitions */
> +#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
> +#define CONFIG_SYS_INIT_RAM_SIZE 0x200000
> +#define CONFIG_SYS_INIT_SP_OFFSET \
> + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
> +#define CONFIG_SYS_INIT_SP_ADDR \
> + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
> +
> +#define CONFIG_SYS_SDRAM_BASE 0x40000000
> +#define PHYS_SDRAM 0x40000000
> +#define PHYS_SDRAM_SIZE 0x40000000 /* Minimum 1 GiB DDR */
> +
> +#define CONFIG_MXC_UART_BASE UART3_BASE_ADDR
> +
> +/* Monitor Command Prompt */
> +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
> +#define CONFIG_SYS_CBSIZE 2048
> +#define CONFIG_SYS_MAXARGS 64
> +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
> +#define CONFIG_SYS_PBSIZE \
> + (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
> +
> +/* PHY needs a longer autonegotiation timeout after reset */
> +#define PHY_ANEG_TIMEOUT 20000
> +#define FEC_QUIRK_ENET_MAC
> +
> +/* USDHC */
> +#define CONFIG_SYS_FSL_USDHC_NUM 2
> +#define CONFIG_SYS_FSL_ESDHC_ADDR 0
> +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
> +
> +#define CONFIG_SYS_I2C_SPEED 100000
> +
> +#if !defined(CONFIG_SPL_BUILD)
> +
> +#define CONFIG_EXTRA_ENV_SETTINGS \
> + "altbootcmd=setenv devpart 2 && run bootcmd ; reset\0" \
> + "bootlimit=3\0" \
> + "devtype=mmc\0" \
> + "devpart=1\0" \
> + /* Give slow devices beyond USB HUB chance to come up. */ \
> + "usb_pgood_delay=2000\0" \
> + "dfu_alt_info=" \
> + /* RAM block at DRAM offset 256..768 MiB */ \
> + "ram ram0=ram ram 0x50000000 0x20000000&" \
> + /* 16 MiB SPI NOR */ \
> + "mtd nor0=sf raw 0x0 0x1000000\0" \
> + "dmo_preboot=" \
> + "sf probe ; " /* Scan for SPI NOR, needed by DFU */ \
> + "run dmo_usb_start_hub ; " \
> + /* Attempt to start USB and Network console */ \
> + "run dmo_usb_cdc_acm_start ; " \
> + "run dmo_netconsole_start\0" \
> + "dmo_update_env=" \
> + "setenv dmo_update_env true ; saveenv ; saveenv\0" \
> + "dmo_usb_cdc_acm_start=" \
> + "if test \"${dmo_usb_cdc_acm_enabled}\" = \"true\" ; then "\
> + /* Ungate IMX8MM_CLK_USB1_CTRL_ROOT */ \
> + "mw 0x303844d0 3 ; " \
> + /* Read USBNC_n_PHY_STATUS BIT(4) VBUS_VLD */ \
> + "setexpr.l usbnc_n_phy_status *0x32e4023c \\\\& 0x8 ; " \
> + /* If USB OTG has valid VBUS, enable CDC ACM */ \
> + "if test \"${usbnc_n_phy_status}\" -eq 8 ; then "\
> + "usb start && " \
> + "setenv stderr ${stderr},usbacm && " \
> + "setenv stdout ${stdout},usbacm && " \
> + "setenv stdin ${stdin},usbacm ; " \
> + "fi ; " \
> + "fi\0" \
> + "dmo_usb_start_hub=" \
> + "i2c dev 1 ; " \
> + /* Reset the USB USB */ \
> + "gpio clear GPIO5_2 ; sleep 0.01 ; " /* t1 > 1us */ \
> + "gpio set GPIO5_2 ; sleep 0.01 ; " /* t5 > 3us */ \
> + /* Write chunks of descriptor into the USB HUB */ \
> + "mw.l 0x7e1000 0x14042417 ; mw.l 0x7e1004 0x9b0bb325 ; "\
> + "mw.l 0x7e1008 0x00000220 ; mw.l 0x7e100c 0x01320100 ; "\
> + "mw.l 0x7e1010 0x00003232 ; mw.l 0x7e1014 0x4d000909 ; "\
> + "i2c write 0x7e1000 0x2c 0x00 0x18 -s ; " \
> + "mw.l 0x7e1000 0x6300690f ; mw.l 0x7e1004 0x6f007200 ; "\
> + "mw.l 0x7e1008 0x68006300 ; mw.l 0x7e100c 0x70006900 ; "\
> + "i2c write 0x7e1000 0x2c 0x18 0x10 -s ; " \
> + "mw.l 0x7e1000 0x53005511 ; mw.l 0x7e1004 0x32004200 ; "\
> + "mw.l 0x7e1008 0x31003500 ; mw.l 0x7e100c 0x42003400 ; "\
> + "mw.l 0x7e1010 0x00006900 ; " \
> + "i2c write 0x7e1000 0x2c 0x54 0x12 -s ; " \
> + "mw.l 0x7e1000 0x00000101 ; " \
> + "i2c write 0x7e1000 0x2c 0xff 0x2 -s\0" \
> + "dmo_netconsole_start=" \
> + "if test \"${dmo_netconsole_enabled}\" = \"true\" ; then "\
> + "setenv autoload false && " \
> + "dhcp && " \
> + "setenv autoload && " \
> + "setenv ncip ${serverip} && " \
> + "setenv stderr ${stderr},nc && " \
> + "setenv stdout ${stdout},nc && " \
> + "setenv stdin ${stdin},nc ; " \
> + "fi"
> +
> +#endif
> +
> +#endif
--
=====================================================================
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
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