[PATCH 10/10] microblaze: cache: use fdt cache size info if available

[Ovidiu Panait]

If CONFIG_CPU_MICROBLAZE is enabled, the cache size and cache line size are
retrieved from the fdt by the microblaze cpu driver. Adjust cache flush
code to use those values if available.

If a cache flush is requested very early in the boot (for example the
flush_cache_all() call in start.S) or before dm is ready, the default size
of CONFIG_XILINX_MICROBLAZE0_DEFAULT_CACHE_SIZE will be used instead.

Signed-off-by: Ovidiu Panait <ovpanait at gmail.com>
---

 arch/microblaze/cpu/cache.c | 45 +++++++++++++++++++++++++++++++++----
 1 file changed, 41 insertions(+), 4 deletions(-)

diff --git a/arch/microblaze/cpu/cache.c b/arch/microblaze/cpu/cache.c
index cce33a6eb5..8b7e212a26 100644
--- a/arch/microblaze/cpu/cache.c
+++ b/arch/microblaze/cpu/cache.c
@@ -9,11 +9,21 @@
 #include <cpu_func.h>
 #include <asm/asm.h>
 #include <asm/cache.h>
+#include <asm/microblaze_cpu.h>
 
 static void __invalidate_icache(ulong addr, ulong size)
 {
 	if (CONFIG_IS_ENABLED(XILINX_MICROBLAZE0_USE_WIC)) {
-		for (int i = 0; i < size; i += 4) {
+		int line_length = 4;
+
+		if (CONFIG_IS_ENABLED(CPU_MICROBLAZE)) {
+			int size = microblaze_cpu_get_cacheline_size(ICACHE);
+
+			if (size > 0)
+				line_length = size;
+		}
+
+		for (int i = 0; i < size; i += line_length) {
 			asm volatile (
 				"wic	%0, r0;"
 				"nop;"
@@ -26,13 +36,31 @@ static void __invalidate_icache(ulong addr, ulong size)
 
 void invalidate_icache_all(void)
 {
-	__invalidate_icache(0, CONFIG_XILINX_MICROBLAZE0_DEFAULT_CACHE_SIZE);
+	int cache_size = CONFIG_XILINX_MICROBLAZE0_DEFAULT_CACHE_SIZE;
+
+	if (CONFIG_IS_ENABLED(CPU_MICROBLAZE)) {
+		int size = microblaze_cpu_get_cache_size(ICACHE);
+
+		if (size >= 0)
+			cache_size = size;
+	}
+
+	__invalidate_icache(0, cache_size);
 }
 
 static void __flush_dcache(ulong addr, ulong size)
 {
 	if (CONFIG_IS_ENABLED(XILINX_MICROBLAZE0_USE_WDC)) {
-		for (int i = 0; i < size; i += 4) {
+		int line_length = 4;
+
+		if (CONFIG_IS_ENABLED(CPU_MICROBLAZE)) {
+			int size = microblaze_cpu_get_cacheline_size(DCACHE);
+
+			if (size > 0)
+				line_length = size;
+		}
+
+		for (int i = 0; i < size; i += line_length) {
 			asm volatile (
 				"wdc.flush	%0, r0;"
 				"nop;"
@@ -53,7 +81,16 @@ void flush_dcache_range(unsigned long start, unsigned long end)
 
 void flush_dcache_all(void)
 {
-	__flush_dcache(0, CONFIG_XILINX_MICROBLAZE0_DEFAULT_CACHE_SIZE);
+	int cache_size = CONFIG_XILINX_MICROBLAZE0_DEFAULT_CACHE_SIZE;
+
+	if (CONFIG_IS_ENABLED(CPU_MICROBLAZE)) {
+		int size = microblaze_cpu_get_cache_size(DCACHE);
+
+		if (size >= 0)
+			cache_size = size;
+	}
+
+	__flush_dcache(0, cache_size);
 }
 
 int dcache_status(void)
-- 
2.25.1