[PATCH v5 1/7] imx8m: add regs used by GPMI

Ariel D'Alessandro ariel.dalessandro at collabora.com
Tue Apr 12 15:31:32 CEST 2022


From: Michael Trimarchi <michael at amarulasolutions.com>

Add regs used by GPMI

Signed-off-by: Michael Trimarchi <michael at amarulasolutions.com>
Signed-off-by: Ariel D'Alessandro <ariel.dalessandro at collabora.com>
Reviewed-by: Fabio Estevam <festevam at gmail.com>
---
 arch/arm/include/asm/arch-imx8m/imx-regs.h | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/include/asm/arch-imx8m/imx-regs.h b/arch/arm/include/asm/arch-imx8m/imx-regs.h
index 45d95a7c197..fb665412465 100644
--- a/arch/arm/include/asm/arch-imx8m/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx8m/imx-regs.h
@@ -58,6 +58,13 @@
 #define SRC_DDRC_RCR_ADDR	0x30391000
 #define SRC_DDRC2_RCR_ADDR	0x30391004
 
+#define APBH_DMA_ARB_BASE_ADDR	0x33000000
+#define APBH_DMA_ARB_END_ADDR	0x33007FFF
+#define MXS_APBH_BASE		APBH_DMA_ARB_BASE_ADDR
+
+#define MXS_GPMI_BASE		(APBH_DMA_ARB_BASE_ADDR + 0x02000)
+#define MXS_BCH_BASE		(APBH_DMA_ARB_BASE_ADDR + 0x04000)
+
 #define DDRC_DDR_SS_GPR0	0x3d000000
 #define DDRC_IPS_BASE_ADDR(X)	(0x3d400000 + ((X) * 0x2000000))
 #define DDR_CSD1_BASE_ADDR	0x40000000
-- 
2.34.1



More information about the U-Boot mailing list