[PATCH v1 2/2] mx6: ddr: Wait before issuing the first MRS cmd

[sbabic at denx.de]

> Wait 1ms before issuing the first MRS command to write DDR3 Mode
> registers.
> There is a requirement to wait a minimum time before issuing command to
> the DDR3 device, according to the JEDEC standard this time is 500us
> (after RESET_n is de-asserted until CKE becomes active) + tXPR (Reset
> CKE Exit time, maximum value 360ns).
> It seems that for some reason this is not enforced by the MMDC
> controller.
> Without this change we experienced random memory initialization failures
> with about 2% boot failure rate on specific problematic boards, after
> this change we were able to do more than 10.000 power-cycle without a
> single failure.
> Fixes: fe0f7f7842e1 ("mx6: add mmdc configuration for MX6Q/MX6DL")
> Signed-off-by: Francesco Dolcini <francesco.dolcini at toradex.com>
> Reviewed-by: Marek Vasut <marex at denx.de>
> Reviewed-by: Fabio Estevam <festevam at denx.de>
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

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