[PATCH v4 09/10] usb: dwc3: Implement .glue_configure for i.MX8MP

[Marek Vasut]

The i.MX8MP glue needs to be configured based on a couple of DT
properties, implement .glue_configure callback to parse those DT
properties and configure the glue accordingly.

Tested-By: Tim Harvey <tharvey at gateworks.com> #imx8mp-venice-gw74xx
Signed-off-by: Marek Vasut <marex at denx.de>
Cc: Angus Ainslie <angus at akkea.ca>
Cc: Bin Meng <bmeng.cn at gmail.com>
Cc: Fabio Estevam <festevam at gmail.com>
Cc: Kunihiko Hayashi <hayashi.kunihiko at socionext.com>
Cc: Michal Simek <michal.simek at xilinx.com>
Cc: Peng Fan <peng.fan at nxp.com>
Cc: Stefano Babic <sbabic at denx.de>
---
V2: Add TB by Tim
V3: Skipped to align the Vx scheme
V4: Rebase on u-boot-imx/master
---
 drivers/usb/dwc3/dwc3-generic.c | 52 +++++++++++++++++++++++++++++++++
 1 file changed, 52 insertions(+)

diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c
index 7e3814207e4..6cf844cb483 100644
--- a/drivers/usb/dwc3/dwc3-generic.c
+++ b/drivers/usb/dwc3/dwc3-generic.c
@@ -223,6 +223,57 @@ struct dwc3_glue_ops {
 			       enum usb_dr_mode mode);
 };
 
+void dwc3_imx8mp_glue_configure(struct udevice *dev, int index,
+				enum usb_dr_mode mode)
+{
+/* USB glue registers */
+#define USB_CTRL0		0x00
+#define USB_CTRL1		0x04
+
+#define USB_CTRL0_PORTPWR_EN	BIT(12) /* 1 - PPC enabled (default) */
+#define USB_CTRL0_USB3_FIXED	BIT(22) /* 1 - USB3 permanent attached */
+#define USB_CTRL0_USB2_FIXED	BIT(23) /* 1 - USB2 permanent attached */
+
+#define USB_CTRL1_OC_POLARITY	BIT(16) /* 0 - HIGH / 1 - LOW */
+#define USB_CTRL1_PWR_POLARITY	BIT(17) /* 0 - HIGH / 1 - LOW */
+	fdt_addr_t regs = dev_read_addr_index(dev, 1);
+	void *base = map_physmem(regs, 0x8, MAP_NOCACHE);
+	u32 value;
+
+	value = readl(base + USB_CTRL0);
+
+	if (dev_read_bool(dev, "fsl,permanently-attached"))
+		value |= (USB_CTRL0_USB2_FIXED | USB_CTRL0_USB3_FIXED);
+	else
+		value &= ~(USB_CTRL0_USB2_FIXED | USB_CTRL0_USB3_FIXED);
+
+	if (dev_read_bool(dev, "fsl,disable-port-power-control"))
+		value &= ~(USB_CTRL0_PORTPWR_EN);
+	else
+		value |= USB_CTRL0_PORTPWR_EN;
+
+	writel(value, base + USB_CTRL0);
+
+	value = readl(base + USB_CTRL1);
+	if (dev_read_bool(dev, "fsl,over-current-active-low"))
+		value |= USB_CTRL1_OC_POLARITY;
+	else
+		value &= ~USB_CTRL1_OC_POLARITY;
+
+	if (dev_read_bool(dev, "fsl,power-active-low"))
+		value |= USB_CTRL1_PWR_POLARITY;
+	else
+		value &= ~USB_CTRL1_PWR_POLARITY;
+
+	writel(value, base + USB_CTRL1);
+
+	unmap_physmem(base, MAP_NOCACHE);
+}
+
+struct dwc3_glue_ops imx8mp_ops = {
+	.glue_configure = dwc3_imx8mp_glue_configure,
+};
+
 void dwc3_ti_glue_configure(struct udevice *dev, int index,
 			    enum usb_dr_mode mode)
 {
@@ -464,6 +515,7 @@ static const struct udevice_id dwc3_glue_ids[] = {
 	{ .compatible = "rockchip,rk3328-dwc3" },
 	{ .compatible = "rockchip,rk3399-dwc3" },
 	{ .compatible = "qcom,dwc3" },
+	{ .compatible = "fsl,imx8mp-dwc3", .data = (ulong)&imx8mp_ops },
 	{ .compatible = "fsl,imx8mq-dwc3" },
 	{ .compatible = "intel,tangier-dwc3" },
 	{ }
-- 
2.35.1