[PATCH 01/11] arm: dts: Add Mercury+ AA1 devicetree

[Paweł Anikiel]

On Mon, Apr 11, 2022 at 8:35 PM Simon Glass <sjg at chromium.org> wrote:
>
> Hi Paweł,
>
> On Fri, 1 Apr 2022 at 06:44, Paweł Anikiel <pan at semihalf.com> wrote:
> >
> > Device tree header for Mercury+ AA1 module
> >
> > Signed-off-by: Paweł Anikiel <pan at semihalf.com>
> > ---
> >  arch/arm/dts/socfpga_mercury_aa1.dtsi | 95 +++++++++++++++++++++++++++
> >  1 file changed, 95 insertions(+)
> >  create mode 100644 arch/arm/dts/socfpga_mercury_aa1.dtsi
> >
>
> Has this been sent to Linux?

Yes, a while ago. It's under
arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dts

>
> > diff --git a/arch/arm/dts/socfpga_mercury_aa1.dtsi b/arch/arm/dts/socfpga_mercury_aa1.dtsi
> > new file mode 100644
> > index 0000000000..7d0bf884a3
> > --- /dev/null
> > +++ b/arch/arm/dts/socfpga_mercury_aa1.dtsi
> > @@ -0,0 +1,95 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Copyright 2022 Google LLC
> > + */
> > +#include "socfpga_arria10.dtsi"
> > +#include "socfpga_arria10-u-boot.dtsi"
> > +
> > +/ {
> > +       model = "Altera SOCFPGA Arria 10";
> > +       compatible = "altr,socfpga-arria10", "altr,socfpga";
> > +
> > +       aliases {
> > +               ethernet0 = &gmac0;
> > +               serial0 = &uart1;
> > +       };
> > +
> > +       chosen {
> > +               stdout-path = "serial0:115200n8";
> > +               firmware-loader = <&fs_loader0>;
> > +       };
> > +
> > +       memory at 0 {
> > +               name = "memory";
> > +               device_type = "memory";
> > +               reg = <0x0 0x80000000>; /* 2GB */
> > +       };
> > +
> > +       fs_loader0: fs-loader {
> > +               u-boot,dm-pre-reloc;
> > +               compatible = "u-boot,fs-loader";
> > +               phandlepart = <&mmc 1>;
> > +       };
> > +};
> > +
> > +&fpga_mgr {
> > +       u-boot,dm-pre-reloc;
> > +       altr,bitstream = "fpga.itb";
> > +};
> > +
> > +&gmac0 {
> > +       phy-mode = "rgmii";
> > +       phy-addr = <0xffffffff>; /* probe for phy addr */
> > +
> > +       txd0-skew-ps = <0>; /* -420ps */
> > +       txd1-skew-ps = <0>; /* -420ps */
> > +       txd2-skew-ps = <0>; /* -420ps */
> > +       txd3-skew-ps = <0>; /* -420ps */
> > +       rxd0-skew-ps = <420>; /* 0ps */
> > +       rxd1-skew-ps = <420>; /* 0ps */
> > +       rxd2-skew-ps = <420>; /* 0ps */
> > +       rxd3-skew-ps = <420>; /* 0ps */
> > +       txen-skew-ps = <0>; /* -420ps */
> > +       txc-skew-ps = <1860>; /* 960ps */
> > +       rxdv-skew-ps = <420>; /* 0ps */
> > +       rxc-skew-ps = <1680>; /* 780ps */
> > +       max-frame-size = <3800>;
> > +};
> > +
> > +&i2c1 {
> > +       u-boot,dm-pre-reloc;
> > +
> > +       atsha204a at 64 {
> > +               u-boot,dm-pre-reloc;
> > +               compatible = "atmel,atsha204a";
> > +               reg = <0x64>;
> > +       };
> > +};
> > +
> > +&main_sdmmc_clk {
> > +       u-boot,dm-pre-reloc;
> > +};
> > +
> > +&mmc {
> > +       cap-sd-highspeed;
> > +       cap-mmc-highspeed;
> > +       broken-cd;
> > +       bus-width = <4>;
> > +       u-boot,dm-pre-reloc;
> > +};
> > +
> > +&peri_sdmmc_clk {
> > +       u-boot,dm-pre-reloc;
> > +};
> > +
> > +&sdmmc_clk {
> > +       u-boot,dm-pre-reloc;
>
> These U-Boot tags should be in the u-boot.dtsi file that you include above.

I believe these are board-specific, so they shouldn't go into
socfpga_arria10-u-boot.dtsi.
I will make a seperate file socfpga_arria10_chameleonv3-u-boot.dtsi
and put them there.

Regards,
Paweł