[PATCH v3] bosch: Add initial board support for ACC
Stefano Babic
sbabic at denx.de
Thu Apr 21 16:53:31 CEST 2022
Hi Philip,
Ci is still broken:
On 19.04.22 16:44, Philip Oberfichtner wrote:
> The Bosch ACC (Air Center Control) Board is based on the i.MX6D.
>
> Signed-off-by: Philip Oberfichtner <pro at denx.de>
>
> ---
>
> Changes in v3:
> - Rename acc to bosch-acc
> - Sync device tree with Linux
>
> Changes in v2:
> - Adapt defconfig and device tree to new bootcount driver
> - Clean up CONFIG_ENV_FLAGS_LIST_STATIC
> - Fix style issues in device trees
> - Migrate CONFIG options to Kconfig
>
>
> This board supports depends on:
> - "Add pmic bootcount driver", patchwork id 291027
> - "crypto/fsl: Fallback to SW sha1/256 is misaligned buffers",
> patchwork id 270524
> - Linux Device Tree patch, see below
>
> The Device Tree is currently being mainlined into Linux. The
> DT in this board support patch will be kept in sync as the DT
> patch for Linux evolves. The Linux patch is tracked under
> http://patchwork.ozlabs.org/project/devicetree-bindings/list/?series=294727
>
> The only difference compared to the Linux DT is the removal of
> usbphynop properties. They are defined in the Linux version of
> imx6qdl.dtsi, but not in the u-boot version.
>
> ---
> arch/arm/dts/Makefile | 1 +
> arch/arm/dts/imx6q-bosch-acc-u-boot.dtsi | 80 ++
> arch/arm/dts/imx6q-bosch-acc.dts | 1036 ++++++++++++++++++++++
> arch/arm/mach-imx/mx6/Kconfig | 15 +
> board/bosch/acc/Kconfig | 19 +
> board/bosch/acc/MAINTAINERS | 9 +
> board/bosch/acc/Makefile | 6 +
> board/bosch/acc/acc.c | 755 ++++++++++++++++
> configs/imx6q_bosch_acc_defconfig | 110 +++
> include/configs/imx6q-bosch-acc.h | 128 +++
> 10 files changed, 2159 insertions(+)
> create mode 100644 arch/arm/dts/imx6q-bosch-acc-u-boot.dtsi
> create mode 100644 arch/arm/dts/imx6q-bosch-acc.dts
> create mode 100644 board/bosch/acc/Kconfig
> create mode 100644 board/bosch/acc/MAINTAINERS
> create mode 100644 board/bosch/acc/Makefile
> create mode 100644 board/bosch/acc/acc.c
> create mode 100644 configs/imx6q_bosch_acc_defconfig
> create mode 100644 include/configs/imx6q-bosch-acc.h
>
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index 644ba961a2..418e0ee655 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -768,6 +768,7 @@ endif
> ifneq ($(CONFIG_MX6Q)$(CONFIG_MX6QDL),)
> dtb-y += \
> imx6-apalis.dtb \
> + imx6q-bosch-acc.dtb \
> imx6q-cm-fx6.dtb \
> imx6q-cubox-i.dtb \
> imx6q-cubox-i-emmc-som-v15.dtb \
> diff --git a/arch/arm/dts/imx6q-bosch-acc-u-boot.dtsi b/arch/arm/dts/imx6q-bosch-acc-u-boot.dtsi
> new file mode 100644
> index 0000000000..37c182d318
> --- /dev/null
> +++ b/arch/arm/dts/imx6q-bosch-acc-u-boot.dtsi
> @@ -0,0 +1,80 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +
> +/* Copyright (C) 2022 Denx Software Engineering GmbH
> + * Philip Oberfichtner <pro at denx.de>
> + */
> +
> +/ {
> + chosen {
> + stdout-path = &uart2;
> + };
> +
> + soc {
> + u-boot,dm-spl;
> +
> + bus at 2000000 {
> + u-boot,dm-spl;
> +
> + spba-bus at 2000000 {
> + u-boot,dm-spl;
> + };
> + };
> +
> + bus at 2100000 {
> + u-boot,dm-spl;
> + };
> + };
> +
> + bootcount {
> + compatible = "u-boot,bootcount-pmic";
> + pmic = <&pmic>;
> + };
> +};
> +
> +&uart1 {
> + u-boot,dm-spl;
> +};
> +
> +&uart2 {
> + u-boot,dm-spl;
> +};
> +
> +&usdhc2 {
> + u-boot,dm-spl;
> +};
> +
> +&usdhc4 {
> + u-boot,dm-spl;
> +};
> +
> +&gpio1 {
> + u-boot,dm-spl;
> +};
> +
> +&gpio2 {
> + u-boot,dm-spl;
> +};
> +
> +&gpio3 {
> + u-boot,dm-spl;
> +};
> +
> +&gpio4 {
> + u-boot,dm-spl;
> +};
> +
> +&gpio5 {
> + u-boot,dm-spl;
> +};
> +
> +&gpio6 {
> + u-boot,dm-spl;
> +};
> +
> +&gpio7 {
> + u-boot,dm-spl;
> +};
> +
> +&wdog1 {
> + u-boot,dm-spl;
> +};
> diff --git a/arch/arm/dts/imx6q-bosch-acc.dts b/arch/arm/dts/imx6q-bosch-acc.dts
> new file mode 100644
> index 0000000000..d0f6ba0cc4
> --- /dev/null
> +++ b/arch/arm/dts/imx6q-bosch-acc.dts
> @@ -0,0 +1,1036 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Support for the i.MX6-based Bosch ACC board.
> + *
> + * Copyright (C) 2016 Garz & Fricke GmbH
> + * Copyright (C) 2018 DENX Software Engineering GmbH, Heiko Schocher <hs at denx.de>
> + * Copyright (C) 2018 DENX Software Engineering GmbH, Niel Fourie <lusus at denx.de>
> + * Copyright (C) 2019-2021 Bosch Thermotechnik GmbH, Matthias Winker <matthias.winker at bosch.com>
> + */
> +
> +/dts-v1/;
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include "imx6q.dtsi"
> +
> +/ {
> + model = "Bosch ACC";
> + compatible = "bosch,imx6q-acc", "fsl,imx6q";
> +
> + aliases {
> + serial0 = &uart2;
> + serial1 = &uart1;
> +
> + i2c0 = &i2c1;
> + i2c1 = &i2c2;
> + i2c2 = &i2c3;
> + /* eMMC is connected to USDHC interface 4, but shall get the name 0 */
> + mmc0 = &usdhc4;
> + /* SC-Cards is connected to USDHC interface 2, but shall get the name 1 */
> + mmc1 = &usdhc2;
> + };
> +
> + backlight {
> + status = "okay";
> +
> + compatible = "pwm-backlight";
> + /* The last value is the PWM period in nano-seconds!
> + * -> 5 kHz = 200 µS = 200.000 ns
> + */
> + pwms = <&pwm1 0 200000>;
> + brightness-levels = <0 61 499 1706 4079 8022 13938 22237 33328 47623 65535>;
> + num-interpolated-steps = <10>;
> + default-brightness-level = <60>;
> + power-supply = <®_lcd0_pwr>;
> + };
> +
> + usb3503_refclk: usb3503_refclk {
> + compatible = "fixed-factor-clock";
> + #clock-cells = <0>;
> +
> + clocks = <&clks IMX6QDL_CLK_CKO2>;
> + clock-div = <1>;
> + clock-mult = <1>;
> + clock-output-names = "12mhz_refclk";
> +
> + assigned-clocks = <&clks IMX6QDL_CLK_CKO>,
> + <&clks IMX6QDL_CLK_CKO2>,
> + <&clks IMX6QDL_CLK_CKO2_SEL>;
> + assigned-clock-parents = <&clks IMX6QDL_CLK_CKO2>,
> + <&clks IMX6QDL_CLK_CKO2_PODF>,
> + <&clks IMX6QDL_CLK_OSC>;
> + assigned-clock-rates = <0>, <12000000>, <0>;
> + };
> +
> + cpus {
> + /* Override operating points with board-specific values */
> + cpu0: cpu at 0 {
> + operating-points = <
> + /* kHz uV */
> + 1200000 1275000
> + 996000 1225000
> + 852000 1225000
> + 792000 1150000
> + 396000 950000
> + >;
> + fsl,soc-operating-points = <
> + /* ARM kHz SOC-PU uV */
> + 1200000 1225000
> + 996000 1175000
> + 852000 1175000
> + 792000 1150000
> + 396000 1150000
> + >;
> + };
> +
> + cpu1: cpu at 1 {
> + operating-points = <
> + /* kHz uV */
> + 1200000 1275000
> + 996000 1225000
> + 852000 1225000
> + 792000 1150000
> + 396000 950000
> + >;
> + fsl,soc-operating-points = <
> + /* ARM kHz SOC-PU uV */
> + 1200000 1225000
> + 996000 1175000
> + 852000 1175000
> + 792000 1150000
> + 396000 1150000
> + >;
> + };
> + };
> +
> + leds {
> + compatible = "pwm-leds";
> +
> + led_red: red {
> + label = "red";
> + max-brightness = <248>;
> + default-state = "off";
> + pwms = <&pwm2 0 500000>;
> + };
> +
> + led_white: white {
> + label = "white";
> + max-brightness = <248>;
> + default-state = "off";
> + pwms = <&pwm3 0 500000>;
> + linux,default-trigger = "heartbeat";
> + };
> + };
> +
> + memory {
> + reg = <0x10000000 0x40000000>;
> + };
> +
> + regulators: regulators {
> + compatible = "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + supply_5P0: regulator at 0 {
> + compatible = "regulator-fixed";
> + reg = <0>;
> + regulator-name = "5P0";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + regulator-always-on;
> + };
> +
> + supply_VIN: regulator at 1 {
> + compatible = "regulator-fixed";
> + reg = <1>;
> + regulator-name = "VIN";
> + regulator-min-microvolt = <4500000>;
> + regulator-max-microvolt = <4500000>;
> + regulator-always-on;
> + vin-supply = <&supply_5P0>;
> + };
> +
> + reg_usb_otg_vbus: regulator at 2 {
> + compatible = "regulator-fixed";
> + reg = <2>;
> + regulator-name = "usb_otg_vbus";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + };
> +
> + reg_usb_h1_vbus: regulator at 3 {
> + compatible = "regulator-fixed";
> + reg = <3>;
> + regulator-name = "usb_h1_vbus";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + regulator-always-on;
> + vin-supply = <&supply_5P0>;
> + };
> +
> + supply_VSNVS_3V0: regulator at 4 {
> + compatible = "regulator-fixed";
> + reg = <4>;
> + regulator-name = "VSNVS_3V0";
> + regulator-min-microvolt = <3000000>;
> + regulator-max-microvolt = <3000000>;
> + regulator-always-on;
> + vin-supply = <&supply_5P0>;
> + };
> +
> + reg_lcd0_pwr: regulator-lcd0-pwr {
> + compatible = "regulator-fixed";
> + regulator-name = "LCD0 POWER";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_lcd_enable>;
> + gpio = <&gpio3 23 GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> + regulator-boot-on;
> + };
> +
> + reg_usb_h2_vbus: regulator at 6 {
> + compatible = "regulator-fixed";
> + reg = <6>;
> + regulator-name = "usb_h2_vbus";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + vin-supply = <&supply_5P0> ;
> + regulator-always-on;
> + };
> +
> + supply_vref_dac: vref_dac {
> + compatible = "regulator-fixed";
> + regulator-name = "vref_dac";
> + regulator-min-microvolt = <20000>;
> + regulator-max-microvolt = <20000>;
> + vin-supply = <&supply_5P0> ;
> + regulator-boot-on;
> + };
> + };
> +
> + reset_gpio_led {
> + compatible = "gpio-leds";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_reset_gpio_led>;
> +
> + reset {
> + label = "red_reset";
> + gpios = <&gpio5 18 0>;
> + default-state = "off";
> + };
> + };
> +
> + soc {
> + aips1: bus at 2000000 {};
> + };
> +};
> +
> +®_arm {
> + vin-supply = <&pmic_sw2>;
> +};
> +
> +®_soc {
> + vin-supply = <&pmic_sw1abc>;
> +};
> +
> +®_vdd1p1 {
> + vin-supply = <&supply_VSNVS_3V0>;
> +};
> +
> +®_vdd2p5 {
> + vin-supply = <&supply_VSNVS_3V0>;
> +};
> +
> +®_vdd3p0 {
> + vin-supply = <&supply_VSNVS_3V0>;
> +};
> +
> +&audmux {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_audmux>;
> + status = "okay";
> +};
> +
> +&fec {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_enet>;
> + status = "okay";
> +
> + clocks = <&clks IMX6QDL_CLK_ENET>,
> + <&clks IMX6QDL_CLK_ENET>,
> + <&clks IMX6QDL_CLK_ENET>,
> + <&clks IMX6QDL_CLK_ENET_REF>;
> + clock-names = "ipg", "ahb", "ptp", "enet_out";
> + phy-mode = "rmii";
> + phy-supply = <&supply_sw4_3V3>;
> + phy-handle = <ðphy>;
> +
> + mdio {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + ethphy: ethernet-phy at 0 {
> + compatible = "ethernet-phy-ieee802.3-c22";
> + reg = <0>;
> + interrupt-parent = <&gpio1>;
> + interrupts = <23 IRQ_TYPE_EDGE_FALLING>;
> + smsc,disable-energy-detect;
> + };
> + };
> +};
> +
> +&gpu_vg {
> + status = "disabled";
> +};
> +
> +&gpu_2d {
> + status = "disabled";
> +};
> +
> +&i2c1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_i2c1>;
> + clock-frequency = <400000>;
> + status = "okay";
> +
> + eeprom: eeprom at 50 {
> + compatible = "atmel,24c32";
> + reg = <0x50>;
> + pagesize = <32>;
> + bytelen = <4096>;
> + bus-id = <0>;
> + flags = <0x80>; /* AT24_FLAG_ADDR16 */
> + };
> +
> + lm75: lm75 at 49 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_lm75>;
> +
> + compatible = "national,lm75b";
> + reg = <0x49>;
> +
> + interrupts = <7 0x4>;
> + interrupt-parent = <&gpio4>;
> + };
> +
> + pmic: pfuze100 at 8 {
> + compatible = "fsl,pfuze100";
> + reg = <0x08>;
> + uboot,bootcounter;
> +
> + VGEN1-supply = <&supply_AUX_3V15>;
> + VGEN2-supply = <&supply_AUX_3V15>;
> + VGEN3-supply = <&supply_sw4_3V3>;
> + VGEN4-supply = <&supply_sw4_3V3>;
> + VGEN5-supply = <&supply_SYS_4V2>;
> + VGEN6-supply = <&supply_SYS_4V2>;
> +
> + VREFDDR-supply = <&supply_DDR_1V5>;
> +
> + SW1AB-supply = <&supply_SYS_4V2>;
> + SW1C-supply = <&supply_SYS_4V2>;
> + SW2-supply = <&supply_SYS_4V2>;
> + SW3A-supply = <&supply_SYS_4V2>;
> + SW3B-supply = <&supply_SYS_4V2>;
> + SW4-supply = <&supply_SYS_4V2>;
> +
> + regulators {
> + /*
> + * VDD_CORE is connected to SW1 ABC
> + * We need to define sw1ab and sw1c, but later it is controlled solely with
> + * sw1c and therefore only this is named "VDD_SOC".
> + * See PMIC datasheet Rev. 18, chapter 6.4.4.3.1: "The feedback and all
> + * other controls are accomplished by use of pin SW1CFB and SW1C control
> + * registers, respectively."
> + * Setting min and max according to SOC datasheet
> + */
> + pmic_sw1abc: sw1c {
> + regulator-name = "VDD_SOC (sw1abc)";
> + regulator-min-microvolt = <1275000>;
> + regulator-max-microvolt = <1500000>;
> + regulator-boot-on;
> + regulator-always-on;
> + regulator-ramp-delay = <6250>;
> +
> + default-voltage = <1300000>;
> + };
> +
> + pmic_sw2: sw2{
> + regulator-name = "VDD_ARM (sw2)";
> +
> + regulator-min-microvolt = <1050000>;
> + regulator-max-microvolt = <1500000>;
> + regulator-boot-on;
> + regulator-always-on;
> + regulator-ramp-delay = <6250>;
> +
> + default-voltage = <1300000>;
> + };
> +
> + pmic_sw3a: sw3a {
> + /* U-Boot sets correct voltage, shall not be touched by the OS */
> + compatible = "regulator-fixed";
> + regulator-name = "DDR_1V5a";
> + regulator-boot-on;
> + regulator-always-on;
> +
> + };
> +
> + supply_DDR_1V5: sw3b {
> + /* U-Boot sets correct voltage, shall not be touched by the OS */
> + compatible = "regulator-fixed";
> + regulator-name = "DDR_1V5b";
> + regulator-boot-on;
> + regulator-always-on;
> +
> + };
> +
> + supply_AUX_3V15: sw4 {
> + regulator-name = "AUX 3V15 (sw4)";
> + regulator-min-microvolt = <800000>;
> + regulator-max-microvolt = <3300000>;
> +
> + default-voltage = <3150000>;
> +
> + };
> +
> + swbst_reg: swbst {
> + status = "disabled";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5150000>;
> + regulator-boot-on;
> + regulator-always-on;
> +
> + };
> +
> + snvs_reg: vsnvs {
> + regulator-min-microvolt = <1200000>;
> + regulator-max-microvolt = <3000000>;
> + regulator-boot-on;
> + regulator-always-on;
> +
> + default-voltage = <3000000>;
> + };
> +
> + vref_reg: vrefddr {
> + regulator-boot-on;
> + regulator-always-on;
> +
> + default-voltage = <675000>;
> + };
> +
> + vgen1_reg: vgen1 {
> + regulator-min-microvolt = <800000>;
> + regulator-max-microvolt = <1550000>;
> + regulator-always-on;
> +
> + default-voltage = <1500000>;
> + };
> +
> + vgen2_reg: vgen2 {
> + regulator-min-microvolt = <800000>;
> + regulator-max-microvolt = <1550000>;
> + regulator-always-on;
> +
> + default-voltage = <1200000>;
> + };
> +
> + vgen3_reg: vgen3 {
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> +
> + default-voltage = <2500000>;
> + };
> +
> + vgen4_reg: vgen4 {
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> + regulator-boot-on;
> +
> + default-voltage = <1800000>;
> + };
> +
> + vgen5_reg: vgen5 {
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> + regulator-boot-on;
> +
> + default-voltage = <2800000>;
> + };
> +
> + vgen6_reg: vgen6 {
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> +
> + default-voltage = <2800000>;
> + };
> +
> + };
> + };
> +
> + rtc: rtcpcf8563 at 51 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_rtc>;
> +
> + compatible = "nxp,pcf8563";
> + reg = <0x51>;
> + };
> +};
> +
> +&i2c2 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_i2c2>;
> + clock-frequency = <100000>;
> + status = "okay";
> +
> + adc101c: ac101c at 54 {
> + compatible = "ti,adc101c";
> + reg = <0x54>;
> + status = "okay";
> + vref-supply = <&supply_vref_dac>;
> + vcc-supply = <&supply_vref_dac>;
> + };
> +
> + ad5602: ad5602 at c {
> + compatible = "adi,ad5602";
> + reg = <0x0c>;
> + status = "okay";
> + vcc-supply = <&supply_vref_dac>;
> + };
> +
> + eeprom_ext: eeprom_ext at 50 {
> + compatible = "atmel,24c32";
> + reg = <0x50>;
> + pagesize = <32>;
> + bytelen = <4096>;
> + bus-id = <1>;
> + flags = <0x80>; /* AT24_FLAG_ADDR16 */
> + };
> +};
> +
> +&i2c3 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_i2c3>;
> + clock-frequency = <400000>;
> + status = "okay";
> +
> + exc3000: exc3000 at 2a {
> + compatible = "eeti,exc3000";
> + reg = <0x2a>;
> +
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_ctouch>;
> +
> + interrupt-parent = <&gpio4>;
> + interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
> +
> + touchscreen-size-x = <4096>;
> + touchscreen-size-y = <4096>;
> +
> + status = "okay";
> + };
> +
> + usb3503: usb3503 at 8 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_usb3503>;
> + status = "okay";
> +
> + compatible = "smsc,usb3503";
> + reg = <0x08>;
> + connect-gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>; /* Old: 0, SS: HIGH */
> + intn-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>; /* Old: 1, SS: HIGH */
> + reset-gpios = <&gpio5 5 GPIO_ACTIVE_LOW>; /* Old: 0, SS: HIGH */
> + initial-mode = <1>;
> +
> + clocks = <&usb3503_refclk>;
> + clock-names = "refclk";
> + refclk-frequency = <12000000>;
> + };
> +
> + vcnl4035: vcnl4035 at 60 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_proximity>;
> + compatible = "vishay,vcnl4035";
> + reg = <0x60>;
> + status = "okay";
> + };
> +};
> +
> +&iomuxc {
> + pinctrl_audmux: audmuxgrp {
> + fsl,pins = <
> + MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0
> + MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x130b0
> + MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x110b0
> + MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0
> + >;
> + };
> +
> + pinctrl_enet: enetgrp {
> + fsl,pins = <
> + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
> + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
> + MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0
> + MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23 0x1b0b0 /* FEC INT */
> + MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0
> + MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x0001B098
> + MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0
> + MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0
> + MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x0001B098
> + MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x0001B098
> + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
> + >;
> + };
> +
> + pinctrl_gpio_export_gpio_fixed_in: pinctrl_gpio_export_gpio_fixed_in_grp {
> + fsl,pins = <
> + MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x80000000 /* CLEAR ALL */
> + MX6QDL_PAD_CSI0_DAT4__GPIO5_IO22 0x80000000 /* DIG_IN_1 */
> + MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23 0x80000000 /* DIG_IN_2 */
> + MX6QDL_PAD_SD3_CMD__GPIO7_IO02 0x80000000 /* PoE */
> + MX6QDL_PAD_SD3_CLK__GPIO7_IO03 0x80000000 /* PoE T2P */
> + >;
> + };
> +
> + pinctrl_reset_gpio_led: pinctrl_reset_gpio_led_pin {
> + fsl,pins = <
> + MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x80000000
> + >;
> + };
> +
> + pinctrl_gpio_export_gpio_fixed_out: pinctrl_gpio_export_gpio_fixed_out_grp {
> + fsl,pins = <
> + MX6QDL_PAD_CSI0_DAT6__GPIO5_IO24 0x0001B0B0 /* DIG_OUT_1 */
> + MX6QDL_PAD_CSI0_DAT7__GPIO5_IO25 0x0001B0B0 /* DIG_OUT_2 */
> + MX6QDL_PAD_DI0_DISP_CLK__GPIO4_IO16 0x0001B0B0 /* nUART_RESET */
> + MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x0001B0B0 /* nETH1_RESET */
> + MX6QDL_PAD_DI0_PIN3__GPIO4_IO19 0x0001B0B0 /* nETH2_RESET */
> + MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x0001B0B0 /* RS485#1_PWR */
> + MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x0001B0B0 /* RS485#2_PWR */
> + MX6QDL_PAD_DISP0_DAT0__GPIO4_IO21 0x0001B0B0 /* RS485#3_PWR */
> + MX6QDL_PAD_DISP0_DAT1__GPIO4_IO22 0x0001B0B0 /* RS485#4_PWR */
> + MX6QDL_PAD_DISP0_DAT6__GPIO4_IO27 0x0001B0B0 /* FEC_RESET_B */
> + MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x0001B0B0 /* AN_IN_PWR */
> + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001B0B0 /* AN_OUT_PWR */
> + MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x0001B0B0 /* nUSBH1_PWR */
> + >;
> + };
> +
> + pinctrl_hog: hoggrp {
> + fsl,pins = <
> + /* not used SD2 and SD3 pins */
> + /* [HYS 1] [100K PU] [PU] [PU EN] [CMOS] [Med. Speed] [40R] [Slow SR] */
> + MX6QDL_PAD_SD3_CLK__GPIO7_IO03 0x0001B0B0
> + MX6QDL_PAD_SD3_CMD__GPIO7_IO02 0x0001B0B0
> + MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x0000B0B1
> + MX6QDL_PAD_EIM_D17__GPIO3_IO17 0x0001B0B0
> + MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x0001B0B0
> + MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x0001B0B0
> + MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x0000B0B1
> + MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x0001B0B0
> + MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x0001B8B1
> + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x0001B8B1
> + MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x000138B1
> + >;
> + };
> +
> + pinctrl_i2c1: i2c1grp {
> + fsl,pins = <
> + MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
> + MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
> + >;
> + };
> +
> + pinctrl_i2c1_gpio: i2c1grp-gpio {
> + fsl,pins = <
> + MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0x80000000
> + MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27 0x80000000
> + >;
> + };
> +
> + pinctrl_i2c2: i2c2grp {
> + fsl,pins = <
> + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b810
> + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b810
> + /* NO SRE | 130 Ohm | SPEED LOW | Open Drain | PKE | PUE | 100k PU | HYS */
> + >;
> + };
> +
> + pinctrl_i2c2_gpio: i2c2grp-gpio {
> + fsl,pins = <
> + MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x80000000
> + MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x80000000
> + >;
> + };
> +
> + pinctrl_i2c3: i2c3grp {
> + fsl,pins = <
> + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
> + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
> + >;
> + };
> + pinctrl_i2c3_gpio: i2c3grp-gpio {
> + fsl,pins = <
> + MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x80000000
> + MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x80000000
> + >;
> + };
> +
> + pinctrl_lcd_enable: lcdenablerp {
> + fsl,pins = <
> + MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000 /* lcd enable */
> + MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x80000000 /* sel6_8 */
> + >;
> + };
> +
> + pinctrl_lm75: lm75grp {
> + fsl,pins = <
> + MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x80000000
> + >;
> + };
> +
> + pinctrl_pfid_0_2: pfid_0_2_grp {
> + fsl,pins = <
> + MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x0001B0B0
> + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x0001B0B0
> + MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x0001B0B0
> + >;
> + };
> +
> + pinctrl_pfid_3_4: pfid_3_4_grp {
> + fsl,pins = <
> + MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x0001B0B0
> + MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x0001B0B0
> + >;
> + };
> +
> + pinctrl_pfid_5_7: pfid_5_7_grp {
> + fsl,pins = <
> + MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x0001B0B0
> + MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x0001B0B0
> + MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x0001B0B0
> + >;
> + };
> +
> + pinctrl_pfid_8_9: pfid_8_9_grp {
> + fsl,pins = <
> + MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x0001B0B0
> + MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x0001B0B0
> + >;
> + };
> +
> + pinctrl_proximity: proximitygrp {
> + fsl,pins = <
> + /* PROXIMITY_INT */
> + MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x80000000
> + >;
> + };
> +
> + pinctrl_pwm1: pwm1grp {
> + fsl,pins = <
> + MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x0001B0B0
> + >;
> + };
> +
> + pinctrl_pwm2: pwm2grp {
> + fsl,pins = <
> + MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x0001B0B0
> + >;
> + };
> +
> + pinctrl_pwm3: pwm3grp {
> + fsl,pins = <
> + MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x0001B0B0
> + >;
> + };
> +
> + pinctrl_pwm4: pwm4grp {
> + fsl,pins = <
> + MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x0001B0B0
> + >;
> + };
> +
> + pinctrl_rtc: rtc-grp {
> + fsl,pins = <
> + MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x80000000 /* RTC INT */
> + >;
> + };
> +
> + pinctrl_ctouch: ctouch-grp {
> + fsl,pins = <
> + MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x80000000 /* CTOUCH_INT */
> + MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x0001B0B0 /* CTOUCH_RESET */
> + >;
> + };
> +
> + pinctrl_uart1: uart1grp {
> + fsl,pins = <
> + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
> + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
> + MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x0001B0B0
> + >;
> + };
> +
> + pinctrl_uart2: uart2grp {
> + fsl,pins = <
> + MX6QDL_PAD_SD3_DAT4__UART2_RX_DATA 0x1b0b1
> + MX6QDL_PAD_SD3_DAT5__UART2_TX_DATA 0x1b0b1
> + MX6QDL_PAD_EIM_D28__UART2_CTS_B 0x1b0b1
> + MX6QDL_PAD_EIM_D29__UART2_RTS_B 0x1b0b1
> + >;
> + };
> +
> + pinctrl_usbh2_idle: usbh2-idle-grp {
> + fsl,pins = <
> + /* 100K Pull-Down, 76_OHM drive strength */
> + MX6QDL_PAD_RGMII_TXC__USB_H2_DATA 0x00013018
> + /* 100K Pull-Down, 76_OHM drive strength */
> + MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x00013018
> + >;
> + };
> +
> + pinctrl_usbh2_active: usbh2-active-grp {
> + fsl,pins = <
> + /* 100K Pull-Down, 76_OHM drive strength */
> + MX6QDL_PAD_RGMII_TXC__USB_H2_DATA 0x00013018
> + /* 47K Pull-Up, 76_OHM drive strength */
> + MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x00017018
> + >;
> + };
> +
> + pinctrl_usb3503: pinctrl_usb3503-grp {
> + fsl,pins = <
> + /* USB Hub REFCLK - No pull-up/pull-down, CMOS output, low speed, 90 Ohm */
> + MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x00000018
> + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000 /* USB INT */
> + MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x0001B0B0 /* USB Reset */
> + MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x80000000 /* USB Connect */
> + >;
> + };
> +
> + pinctrl_usbotg: usbotggrp {
> + fsl,pins = <
> + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
> + >;
> + };
> +
> + pinctrl_usdhc2: usdhc2grp {
> + /* CMD and DATA0..3 have external pull-up, CLK does not need a pull-up.
> + * CLK signal is half the speed than the others (52 MHz compared to 104 MHz)
> + */
> + fsl,pins = <
> + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x00017069
> + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x00010038
> + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x00017069
> + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x00017069
> + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x00017069
> + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x00017069
> + MX6QDL_PAD_GPIO_4__SD2_CD_B 0x0001B0B0
> + >;
> + };
> +
> + pinctrl_usdhc4: usdhc4grp {
> + /* CMD has external pull-up, DATA0..7 within eMMC, CLK does not need a pull-up.
> + * CLK signal is half the speed than the others (52 MHz compared to 104 MHz)
> + */
> + fsl,pins = <
> + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x00017059
> + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x00010059
> + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x00017059
> + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x00017059
> + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x00017059
> + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x00017059
> + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x00017059
> + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x00017059
> + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x00017059
> + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x00017059
> + >;
> + };
> +
> + pinctrl_wdog1: wdoggrp {
> + fsl,pins = <
> + MX6QDL_PAD_GPIO_9__WDOG1_B 0x1b0b0
> + >;
> + };
> +};
> +
> +&ldb {
> + status = "okay";
> +
> + lvds0: lvds-channel at 0 {
> + fsl,data-mapping = "spwg";
> + fsl,data-width = <24>;
> + status = "okay";
> +
> + display-timings {
> + native-mode = <&lvds0_timing0>;
> + lvds0_timing0: hsd100pxn1 {
> + clock-frequency = <79479000>;
> + hactive = <1280>;
> + vactive = <800>;
> + hback-porch = <100>;
> + hfront-porch = <100>;
> + vback-porch = <5>;
> + vfront-porch = <5>;
> + hsync-len = <24>;
> + vsync-len = <3>;
> + hsync-active = <0>;
> + vsync-active = <0>;
> + de-active = <1>;
> + pixelclk-active = <1>;
> + };
> + };
> + };
> +};
> +
> +&pmu {
> + interrupt-affinity = <&{/cpus/cpu at 0}>,
> + <&{/cpus/cpu at 1}>;
> +};
> +
> +&pwm1 {
> + #pwm-cells = <2>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_pwm1>;
> + status = "okay";
> +};
> +
> +&pwm2 {
> + #pwm-cells = <2>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_pwm2>;
> + status = "okay";
> +};
> +
> +&pwm3 {
> + #pwm-cells = <2>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_pwm3>;
> + status = "okay";
> + linux,default-trigger = "heartbeat";
> +};
> +
> +&pwm4 {
> + #pwm-cells = <2>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_pwm4>;
> + status = "okay";
> +};
> +
> +®ulators {
> + supply_sw4_3V3: regulator at 8 {
> + compatible = "regulator-fixed";
> + reg = <8>;
> + regulator-name = "SW4_3V3";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> + vin-supply = <&supply_5P0>;
> + };
> +
> + supply_SYS_4V2: regulator at 9 {
> + compatible = "regulator-fixed";
> + reg = <9>;
> + regulator-name = "SYS_4V2";
> + regulator-min-microvolt = <4200000>;
> + regulator-max-microvolt = <4200000>;
> + regulator-always-on;
> + vin-supply = <&supply_5P0>;
> + };
> +};
> +
> +&sdma {
> + fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
> + iram = <&ocram>;
> +};
> +
> +&uart1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart1>;
> + status = "okay";
> +
> + rts-gpios = <&gpio7 8 0>;
> + linux,rs485-enabled-at-boot-time;
> + rs485-rx-during-tx;
> +};
> +
> +&uart2 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart2>;
> + fsl,uart-has-rtscts;
> + status = "okay";
> +};
> +
> +&usbh1 {
> + vbus-supply = <®_usb_h1_vbus>;
> + status = "okay";
> +};
> +
> +&usbh2 {
> + pinctrl-names = "idle", "active";
> + pinctrl-0 = <&pinctrl_usbh2_idle>;
> + pinctrl-1 = <&pinctrl_usbh2_active>;
> + status = "okay";
> +
> + vbus-supply = <®_usb_h2_vbus>;
> + osc-clkgate-delay = <0x3>;
> +
> + pad-supply = <&vgen2_reg>;
> +};
> +
> +&usbotg {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_usbotg>;
> + status = "okay";
> +
> + vbus-supply = <®_usb_otg_vbus>;
> + disable-over-current;
> + dr_mode = "otg";
> + srp-disable;
> + hnp-disable;
> + adp-disable;
> +};
> +
> +/* sdcard */
> +&usdhc2 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_usdhc2>;
> + status = "okay";
> +
> + cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
> + no-1-8-v;
> + keep-power-in-suspend;
> + enable-sdio-wakeup;
> + voltage-ranges = <3300 3300>;
> + vmmc-supply = <&supply_sw4_3V3>;
> + fsl,wp-controller;
> +};
> +
> +/* emmc */
> +&usdhc4 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_usdhc4>;
> + status = "okay";
> +
> + bus-width = <8>;
> + non-removable;
> + no-1-8-v;
> + keep-power-in-suspend;
> + voltage-ranges = <3300 3300>;
> + vmmc-supply = <&supply_sw4_3V3>;
> + fsl,wp-controller;
> +};
> +
> +&wdog1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_wdog1>;
> + fsl,ext-reset-output;
> + status = "okay";
> + timeout-sec=<10>;
> +};
> +
> diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig
> index 98df4d4e42..995b4b2426 100644
> --- a/arch/arm/mach-imx/mx6/Kconfig
> +++ b/arch/arm/mach-imx/mx6/Kconfig
> @@ -345,6 +345,20 @@ config TARGET_MX6Q_ENGICAM
> select SUPPORT_SPL
> imply CMD_DM
>
> +config TARGET_MX6Q_ACC
> + bool "Support for Bosch ACC board"
> + depends on MX6QDL
> + select BOARD_LATE_INIT
> + select OF_CONTROL
> + select SPL_OF_LIBFDT
> + select DM
> + select DM_ETH
> + select DM_GPIO
> + select DM_I2C
> + select DM_MMC
> + select DM_THERMAL
> + select SUPPORT_SPL
> +
> config TARGET_MX6SABREAUTO
> bool "mx6sabreauto"
> depends on MX6QDL
> @@ -674,6 +688,7 @@ source "board/freescale/mx6sxsabresd/Kconfig"
> source "board/freescale/mx6sxsabreauto/Kconfig"
> source "board/freescale/mx6ul_14x14_evk/Kconfig"
> source "board/freescale/mx6ullevk/Kconfig"
> +source "board/bosch/acc/Kconfig"
> source "board/grinn/liteboard/Kconfig"
> source "board/phytec/pcm058/Kconfig"
> source "board/phytec/pcl063/Kconfig"
> diff --git a/board/bosch/acc/Kconfig b/board/bosch/acc/Kconfig
> new file mode 100644
> index 0000000000..da54d96e40
> --- /dev/null
> +++ b/board/bosch/acc/Kconfig
> @@ -0,0 +1,19 @@
> +if TARGET_MX6Q_ACC
> +
> +config SYS_VENDOR
> + default "bosch"
> +
> +config SYS_BOARD
> + default "acc"
> +
> +config SYS_CONFIG_NAME
> + default "imx6q-bosch-acc"
> +
> +config SYS_BOOT_EMMC
> + bool "Boot from EMMC"
> + default y
> + help
> + Say N here if you want to boot from SD card or microUSB.
> + Say Y to boot from eMMC.
> +
> +endif
> diff --git a/board/bosch/acc/MAINTAINERS b/board/bosch/acc/MAINTAINERS
> new file mode 100644
> index 0000000000..1b88003712
> --- /dev/null
> +++ b/board/bosch/acc/MAINTAINERS
> @@ -0,0 +1,9 @@
> +MX6Q_ACC
> +M: Matthias Winker <matthias.winker at de.bosch.com>
> +M: Philip Oberfichtner <pro at denx.de>
> +S: Maintained
> +F: board/bosch/acc
> +F: include/configs/imx6q-bosch-acc.h
> +F: configs/imx6q_bosch_acc_defconfig
> +F: arch/arm/dts/imx6q-bosch-acc.dts
> +F: arch/arm/dts/imx6q-bosch-acc-u-boot.dts
> diff --git a/board/bosch/acc/Makefile b/board/bosch/acc/Makefile
> new file mode 100644
> index 0000000000..d425a677bc
> --- /dev/null
> +++ b/board/bosch/acc/Makefile
> @@ -0,0 +1,6 @@
> +# Copyright (C) 2017
> +#
> +# SPDX-License-Identifier: GPL-2.0+
> +#
> +
> +obj-y := acc.o
> diff --git a/board/bosch/acc/acc.c b/board/bosch/acc/acc.c
> new file mode 100644
> index 0000000000..dbc03c9371
> --- /dev/null
> +++ b/board/bosch/acc/acc.c
> @@ -0,0 +1,755 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (c) 2017 DENX Software Engineering GmbH, Heiko Schocher <hs at denx.de>
> + * Copyright (c) 2019 Bosch Thermotechnik GmbH
> + * Copyright (c) 2022 DENX Software Engineering GmbH, Philip Oberfichtner <pro at denx.de>
> + */
> +
> +#include <common.h>
> +#include <bootstage.h>
> +#include <dm.h>
> +#include <dm/platform_data/serial_mxc.h>
> +#include <dm/device-internal.h>
> +#include <env.h>
> +#include <env_internal.h>
> +#include <hang.h>
> +#include <init.h>
> +#include <linux/delay.h>
> +#include <mmc.h>
> +
> +#include <asm/io.h>
> +#include <asm/gpio.h>
> +#include <linux/sizes.h>
> +
> +#include <asm/arch/clock.h>
> +#include <asm/arch/crm_regs.h>
> +#include <asm/arch/iomux.h>
> +#include <asm/arch/mx6-pins.h>
> +#include <asm/arch/sys_proto.h>
> +#include <asm/mach-imx/iomux-v3.h>
> +#include <usb.h>
> +#include <usb/ehci-ci.h>
> +#include <fuse.h>
> +
> +#include <watchdog.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +#define GPIO_ACC_PLAT_DETECT IMX_GPIO_NR(5, 9)
> +#define GPIO_ACC_RAM_VOLT_DETECT IMX_GPIO_NR(5, 0)
> +#define GPIO_BUZZER IMX_GPIO_NR(1, 18)
> +#define GPIO_LAN1_RESET IMX_GPIO_NR(4, 27)
> +#define GPIO_LAN2_RESET IMX_GPIO_NR(4, 19)
> +#define GPIO_LAN3_RESET IMX_GPIO_NR(4, 18)
> +#define GPIO_USB_HUB_RESET IMX_GPIO_NR(5, 5)
> +#define GPIO_EXP_RS485_RESET IMX_GPIO_NR(4, 16)
> +#define GPIO_TOUCH_RESET IMX_GPIO_NR(1, 20)
> +
> +#define BOARD_INFO_MAGIC 0x19730517
> +
> +struct board_info {
> + int magic;
> + int board;
> + int rev;
> +};
> +
> +static struct board_info *detect_board(void);
> +
> +#define PFID_BOARD_ACC 0xe
> +
> +static const char * const name_board[] = {
> + [PFID_BOARD_ACC] = "ACC",
> +};
> +
> +#define PFID_REV_22 0x8
> +#define PFID_REV_21 0x9
> +#define PFID_REV_20 0xa
> +#define PFID_REV_14 0xb
> +#define PFID_REV_13 0xc
> +#define PFID_REV_12 0xd
> +#define PFID_REV_11 0xe
> +#define PFID_REV_10 0xf
> +
> +static const char * const name_revision[] = {
> + [0 ... PFID_REV_10] = "Unknown",
> + [PFID_REV_10] = "1.0",
> + [PFID_REV_11] = "1.1",
> + [PFID_REV_12] = "1.2",
> + [PFID_REV_13] = "1.3",
> + [PFID_REV_14] = "1.4",
> + [PFID_REV_20] = "2.0",
> + [PFID_REV_21] = "2.1",
> + [PFID_REV_22] = "2.2",
> +};
> +
> +/*
> + * NXP Reset Default: 0x0001B0B0
> + * - Schmitt trigger input (PAD_CTL_HYS)
> + * - 100K Ohm Pull Up (PAD_CTL_PUS_100K_UP)
> + * - Pull Enabled (PAD_CTL_PUE)
> + * - Pull/Keeper Enabled (PAD_CTL_PKE)
> + * - CMOS output (No PAD_CTL_ODE)
> + * - Medium Speed (PAD_CTL_SPEED_MED)
> + * - 40 Ohm drive strength (PAD_CTL_DSE_40ohm)
> + * - Slow (PAD_CTL_SRE_SLOW)
> + */
> +
> +/* Input, no pull up/down: 0x0x000100B0 */
> +#define GPIN_PAD_CTRL (PAD_CTL_HYS \
> + | PAD_CTL_SPEED_MED \
> + | PAD_CTL_DSE_40ohm \
> + | PAD_CTL_SRE_SLOW)
> +
> +/* Input, pull up: 0x0x0001B0B0 */
> +#define GPIN_PU_PAD_CTRL (PAD_CTL_HYS \
> + | PAD_CTL_PUS_100K_UP \
> + | PAD_CTL_PUE \
> + | PAD_CTL_PKE \
> + | PAD_CTL_SPEED_MED \
> + | PAD_CTL_DSE_40ohm \
> + | PAD_CTL_SRE_SLOW)
> +
> +/* Input, pull down: 0x0x000130B0 */
> +#define GPIN_PD_PAD_CTRL (PAD_CTL_HYS \
> + | PAD_CTL_PUS_100K_DOWN \
> + | PAD_CTL_PUE \
> + | PAD_CTL_PKE \
> + | PAD_CTL_SPEED_MED \
> + | PAD_CTL_DSE_40ohm \
> + | PAD_CTL_SRE_SLOW)
> +
> +static const iomux_v3_cfg_t board_detect_pads[] = {
> + /* Platform detect */
> + IOMUX_PADS(PAD_DISP0_DAT15__GPIO5_IO09 | MUX_PAD_CTRL(GPIN_PAD_CTRL)),
> + /* RAM Volt detect */
> + IOMUX_PADS(PAD_EIM_WAIT__GPIO5_IO00 | MUX_PAD_CTRL(GPIN_PAD_CTRL)),
> + /* PFID 0..9 */
> + IOMUX_PADS(PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(GPIN_PAD_CTRL)),
> + IOMUX_PADS(PAD_NANDF_D1__GPIO2_IO01 | MUX_PAD_CTRL(GPIN_PAD_CTRL)),
> + IOMUX_PADS(PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(GPIN_PAD_CTRL)),
> + IOMUX_PADS(PAD_NANDF_D3__GPIO2_IO03 | MUX_PAD_CTRL(GPIN_PAD_CTRL)),
> + IOMUX_PADS(PAD_NANDF_D4__GPIO2_IO04 | MUX_PAD_CTRL(GPIN_PAD_CTRL)),
> + IOMUX_PADS(PAD_NANDF_D5__GPIO2_IO05 | MUX_PAD_CTRL(GPIN_PAD_CTRL)),
> + IOMUX_PADS(PAD_NANDF_D6__GPIO2_IO06 | MUX_PAD_CTRL(GPIN_PAD_CTRL)),
> + IOMUX_PADS(PAD_NANDF_D7__GPIO2_IO07 | MUX_PAD_CTRL(GPIN_PAD_CTRL)),
> + IOMUX_PADS(PAD_NANDF_CS3__GPIO6_IO16 | MUX_PAD_CTRL(GPIN_PAD_CTRL)),
> + IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(GPIN_PAD_CTRL)),
> + /* Manufacturer */
> + IOMUX_PADS(PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(GPIN_PAD_CTRL)),
> + /* Redundant */
> + IOMUX_PADS(PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(GPIN_PU_PAD_CTRL))
> +};
> +
> +static int gpio_acc_pfid[] = {
> + IMX_GPIO_NR(2, 0),
> + IMX_GPIO_NR(2, 1),
> + IMX_GPIO_NR(2, 2),
> + IMX_GPIO_NR(2, 3),
> + IMX_GPIO_NR(2, 4),
> + IMX_GPIO_NR(6, 14),
> + IMX_GPIO_NR(6, 15),
> + IMX_GPIO_NR(2, 5),
> + IMX_GPIO_NR(2, 6),
> + IMX_GPIO_NR(2, 7),
> + IMX_GPIO_NR(6, 16),
> + IMX_GPIO_NR(5, 4),
> +};
> +
> +static int init_gpio(int nr)
> +{
> + int ret;
> +
> + ret = gpio_request(nr, "");
> + if (ret != 0) {
> + printf("Could not request gpio nr: %d\n", nr);
> + hang();
> + }
> + ret = gpio_direction_input(nr);
> + if (ret != 0) {
> + printf("Could not set gpio nr: %d to input\n", nr);
> + hang();
> + }
> + return 0;
> +}
> +
> +/*
> + * We want to detect the board type only once in SPL,
> + * so we store the board_info struct at beginning in IRAM.
> + *
> + * U-Boot itself can read it also, and do not need again
> + * to detect board type.
> + *
> + */
> +static struct board_info *detect_board(void)
> +{
> + struct board_info *binfo = (struct board_info *)IRAM_BASE_ADDR;
> + int i;
> +
> + if (binfo->magic == BOARD_INFO_MAGIC)
> + return binfo;
> +
> + puts("Board: ");
> + SETUP_IOMUX_PADS(board_detect_pads);
> + init_gpio(GPIO_ACC_PLAT_DETECT);
> + if (gpio_get_value(GPIO_ACC_PLAT_DETECT)) {
> + puts("not supported");
> + hang();
> + } else {
> + puts("Bosch ");
> + }
> +
> + for (i = 0; i < sizeof(gpio_acc_pfid) / sizeof(int); i++)
> + init_gpio(gpio_acc_pfid[i]);
> +
> + binfo->board = gpio_get_value(gpio_acc_pfid[0]) << 0 |
> + gpio_get_value(gpio_acc_pfid[1]) << 1 |
> + gpio_get_value(gpio_acc_pfid[2]) << 2 |
> + gpio_get_value(gpio_acc_pfid[11]) << 3;
> + printf("%s ", name_board[binfo->board]);
> +
> + binfo->rev = gpio_get_value(gpio_acc_pfid[7]) << 0 |
> + gpio_get_value(gpio_acc_pfid[8]) << 1 |
> + gpio_get_value(gpio_acc_pfid[9]) << 2 |
> + gpio_get_value(gpio_acc_pfid[10]) << 3;
> + printf("rev: %s\n", name_revision[binfo->rev]);
> +
> + binfo->magic = BOARD_INFO_MAGIC;
> +
> + return binfo;
> +}
> +
> +static void unset_early_gpio(void)
> +{
> + init_gpio(GPIO_LAN1_RESET);
> + init_gpio(GPIO_LAN2_RESET);
> + init_gpio(GPIO_LAN3_RESET);
> + init_gpio(GPIO_USB_HUB_RESET);
> + init_gpio(GPIO_EXP_RS485_RESET);
> + init_gpio(GPIO_TOUCH_RESET);
> +
> + gpio_set_value(GPIO_LAN1_RESET, 1);
> + gpio_set_value(GPIO_LAN2_RESET, 1);
> + gpio_set_value(GPIO_LAN3_RESET, 1);
> + gpio_set_value(GPIO_USB_HUB_RESET, 1);
> + gpio_set_value(GPIO_EXP_RS485_RESET, 1);
> + gpio_set_value(GPIO_TOUCH_RESET, 1);
> +}
> +
> +enum env_location env_get_location(enum env_operation op, int prio)
> +{
> + if (op == ENVOP_SAVE || op == ENVOP_ERASE)
> + return ENVL_MMC;
> +
> + switch (prio) {
> + case 0:
> + return ENVL_NOWHERE;
> +
> + case 1:
> + return ENVL_MMC;
> + }
> +
> + return ENVL_UNKNOWN;
> +}
> +
> +int board_late_init(void)
> +{
> + struct board_info *binfo = detect_board();
> +
> + switch (binfo->board) {
> + case PFID_BOARD_ACC:
> + env_set("bootconf", "conf-imx6q-bosch-acc.dtb");
> + break;
> + default:
> + printf("Unknown board %d\n", binfo->board);
> + break;
> + }
> +
> + unset_early_gpio();
> +
> + return 0;
> +}
> +
> +int board_init(void)
> +{
> + /* Address of boot parameters */
> + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
> +
> + return 0;
> +}
> +
> +int dram_init(void)
> +{
> + gd->ram_size = imx_ddr_size();
> +
> + return 0;
> +}
> +
> +#if IS_ENABLED(CONFIG_SPL_BUILD)
> +#include <asm/arch/crm_regs.h>
> +#include <asm/arch/imx-regs.h>
> +#include <asm/arch/iomux.h>
> +#include <asm/arch/mx6-ddr.h>
> +#include <asm/arch/mx6-pins.h>
> +#include <asm/arch/sys_proto.h>
> +#include <spl.h>
> +
> +/* Early
> + * - Buzzer -> GPIO IN, Pull-Down (PWM enabled by Kernel later-on, lacks of an
> + * external pull-down resistor)
> + * - Touch clean reset on every boot
> + * - Ethernet(s), USB Hub, Expansion RS485 -> Clean reset on each u-boot init
> + */
> +static const iomux_v3_cfg_t early_pads[] = {
> + IOMUX_PADS(PAD_SD1_CMD__GPIO1_IO18 | MUX_PAD_CTRL(GPIN_PD_PAD_CTRL)), /* Buzzer PWM */
> + IOMUX_PADS(PAD_DISP0_DAT6__GPIO4_IO27 | MUX_PAD_CTRL(GPIN_PD_PAD_CTRL)), /* #FEC_RESET_B */
> + IOMUX_PADS(PAD_DI0_PIN2__GPIO4_IO18 | MUX_PAD_CTRL(GPIN_PD_PAD_CTRL)), /* #ETH1_RESET */
> + IOMUX_PADS(PAD_DI0_PIN3__GPIO4_IO19 | MUX_PAD_CTRL(GPIN_PD_PAD_CTRL)), /* #ETH2_RESET */
> + IOMUX_PADS(PAD_DISP0_DAT11__GPIO5_IO05 | MUX_PAD_CTRL(GPIN_PD_PAD_CTRL)), /* #USB Reset */
> + IOMUX_PADS(PAD_DI0_DISP_CLK__GPIO4_IO16 | MUX_PAD_CTRL(GPIN_PD_PAD_CTRL)), /* #UART_RESET */
> + IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20 | MUX_PAD_CTRL(GPIN_PD_PAD_CTRL)), /* #CTOUCH_RESET */
> +};
> +
> +static void setup_iomux_early(void)
> +{
> + SETUP_IOMUX_PADS(early_pads);
> +}
> +
> +static void set_early_gpio(void)
> +{
> + init_gpio(GPIO_BUZZER);
> + init_gpio(GPIO_LAN1_RESET);
> + init_gpio(GPIO_LAN2_RESET);
> + init_gpio(GPIO_LAN3_RESET);
> + init_gpio(GPIO_USB_HUB_RESET);
> + init_gpio(GPIO_EXP_RS485_RESET);
> + init_gpio(GPIO_TOUCH_RESET);
> +
> + /* Reset signals are active low */
> + gpio_set_value(GPIO_BUZZER, 0);
> + gpio_set_value(GPIO_LAN1_RESET, 0);
> + gpio_set_value(GPIO_LAN2_RESET, 0);
> + gpio_set_value(GPIO_LAN3_RESET, 0);
> + gpio_set_value(GPIO_USB_HUB_RESET, 0);
> + gpio_set_value(GPIO_EXP_RS485_RESET, 0);
> + gpio_set_value(GPIO_TOUCH_RESET, 0);
> +}
> +
> +/* UART */
> +#define UART_PAD_CTRL \
> + (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
> + PAD_CTL_SRE_FAST | PAD_CTL_HYS)
> +
> +#undef UART_PAD_CTRL
> +#define UART_PAD_CTRL 0x1b0b1
> +static const iomux_v3_cfg_t uart2_pads[] = {
> + IOMUX_PADS(PAD_SD3_DAT4__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
> + IOMUX_PADS(PAD_SD3_DAT5__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
> + IOMUX_PADS(PAD_SD3_CMD__UART2_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL)),
> + IOMUX_PADS(PAD_SD3_CLK__UART2_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL)),
> +};
> +
> +static void setup_iomux_uart(void)
> +{
> + SETUP_IOMUX_PADS(uart2_pads);
> +}
> +
> +void spl_board_init(void)
> +{
> +}
> +
> +static const struct mx6dq_iomux_ddr_regs acc_mx6d_ddr_ioregs = {
> + .dram_sdclk_0 = 0x00008038,
> + .dram_sdclk_1 = 0x00008038,
> + .dram_cas = 0x00008028,
> + .dram_ras = 0x00008028,
> + .dram_reset = 0x00000028,
> + .dram_sdcke0 = 0x00003000,
> + .dram_sdcke1 = 0x00003000,
> + .dram_sdba2 = 0x00008000,
> + .dram_sdodt0 = 0x00000028,
> + .dram_sdodt1 = 0x00000028,
> + .dram_sdqs0 = 0x00008038,
> + .dram_sdqs1 = 0x00008038,
> + .dram_sdqs2 = 0x00008038,
> + .dram_sdqs3 = 0x00008038,
> + .dram_sdqs4 = 0x00008038,
> + .dram_sdqs5 = 0x00008038,
> + .dram_sdqs6 = 0x00008038,
> + .dram_sdqs7 = 0x00008038,
> + .dram_dqm0 = 0x00008038,
> + .dram_dqm1 = 0x00008038,
> + .dram_dqm2 = 0x00008038,
> + .dram_dqm3 = 0x00008038,
> + .dram_dqm4 = 0x00008038,
> + .dram_dqm5 = 0x00008038,
> + .dram_dqm6 = 0x00008038,
> + .dram_dqm7 = 0x00008038,
> +};
> +
> +static const struct mx6dq_iomux_grp_regs acc_mx6d_grp_ioregs = {
> + .grp_ddr_type = 0x000C0000,
> + .grp_ddrmode_ctl = 0x00020000,
> + .grp_ddrpke = 0x00000000,
> + .grp_addds = 0x00000030,
> + .grp_ctlds = 0x00000028,
> + .grp_ddrmode = 0x00020000,
> + .grp_b0ds = 0x00000038,
> + .grp_b1ds = 0x00000038,
> + .grp_b2ds = 0x00000038,
> + .grp_b3ds = 0x00000038,
> + .grp_b4ds = 0x00000038,
> + .grp_b5ds = 0x00000038,
> + .grp_b6ds = 0x00000038,
> + .grp_b7ds = 0x00000038,
> +};
> +
> +static const struct mx6_mmdc_calibration acc_mx6d_mmdc_calib = {
> + .p0_mpwldectrl0 = 0x0020001F,
> + .p0_mpwldectrl1 = 0x00280021,
> + .p1_mpwldectrl0 = 0x00120028,
> + .p1_mpwldectrl1 = 0x000D001F,
> + .p0_mpdgctrl0 = 0x43340342,
> + .p0_mpdgctrl1 = 0x03300325,
> + .p1_mpdgctrl0 = 0x4334033E,
> + .p1_mpdgctrl1 = 0x03280270,
> + .p0_mprddlctl = 0x46373B3E,
> + .p1_mprddlctl = 0x3B383544,
> + .p0_mpwrdlctl = 0x36383E40,
> + .p1_mpwrdlctl = 0x4030433A,
> +};
> +
> +/* Micron MT41K128M16JT-125 (standard - 1600,CL=11)
> + * !!! i.MX6 does NOT support data rates higher than DDR3-1066 !!!
> + * So this setting is actually invalid!
> + *
> +static const struct mx6_ddr3_cfg acc_mx6d_mem_ddr3_1600 = {
> + .mem_speed = 1600,
> + .density = 2,
> + .width = 16,
> + .banks = 8,
> + .rowaddr = 14,
> + .coladdr = 10,
> + .pagesz = 2,
> + .trcd = 1375,
> + .trcmin = 4875,
> + .trasmin = 3500,
> + .SRT = 0,
> +};
> + */
> +
> +/* Micron MT41K128M16JT-125 is backward-compatible with 1333,CL=9 (-15E) and 1066,CL=7 (-187E)
> + * Lowering to 1066 saves on ACC ~0.25 Watt at DC In with negligible performance loss
> + * width set to 64, as four chips are used on acc (4 * 16 = 64)
> + */
> +static const struct mx6_ddr3_cfg acc_mx6d_mem_ddr3_1066 = {
> + .mem_speed = 1066,
> + .density = 2,
> + .width = 64,
> + .banks = 8,
> + .rowaddr = 14,
> + .coladdr = 10,
> + .pagesz = 2,
> + .trcd = 1313, // 13.125ns
> + .trcmin = 5063, // 50.625ns
> + .trasmin = 3750, // 37.5ns
> + .SRT = 0, // Set to 1 for temperatures above 85°C
> +};
> +
> +static const struct mx6_ddr_sysinfo acc_mx6d_ddr_info = {
> + .ddr_type = DDR_TYPE_DDR3,
> + /* width of data bus:0=16,1=32,2=64 */
> + .dsize = 2,
> + .cs_density = 32, /* 32Gb per CS */
> + .ncs = 1, /* single chip select */
> + .cs1_mirror = 0,
> + .rtt_wr = 1, /* DDR3_RTT_60_OHM, RTT_Wr = RZQ/4 */
> + .rtt_nom = 1, /* DDR3_RTT_60_OHM, RTT_Nom = RZQ/4 */
> + .walat = 0, /* Write additional latency */
> + .ralat = 5, /* Read additional latency */
> + .mif3_mode = 3, /* Command prediction working mode */
> + .bi_on = 1, /* Bank interleaving enabled */
> + .sde_to_rst = 0x33, /* 14 cycles, 200us (JEDEC default) */
> + .rst_to_cke = 0x33, /* 33 cycles, 500us (JEDEC default) */
> +};
> +
> +#define ACC_SPREAD_SPECTRUM_STOP 0x0fa
> +#define ACC_SPREAD_SPECTRUM_STEP 0x001
> +#define ACC_SPREAD_SPECTRUM_DENOM 0x190
> +
> +static void ccgr_init(void)
> +{
> + struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
> +
> + /* Turn clocks on/off */
> + writel(0x00C0000F, &ccm->CCGR0);
> + writel(0x0030FC00, &ccm->CCGR1);
> + writel(0x03FF0033, &ccm->CCGR2);
> + writel(0x3FF3300F, &ccm->CCGR3);
> + writel(0x0003C300, &ccm->CCGR4);
> + writel(0x0F3000C3, &ccm->CCGR5);
> + writel(0x00000FFF, &ccm->CCGR6);
> +
> + /* Enable spread spectrum */
> + writel(BM_ANADIG_PLL_528_SS_ENABLE |
> + BF_ANADIG_PLL_528_SS_STOP(ACC_SPREAD_SPECTRUM_STOP) |
> + BF_ANADIG_PLL_528_SS_STEP(ACC_SPREAD_SPECTRUM_STEP),
> + &ccm->analog_pll_528_ss);
> +
> + writel(BF_ANADIG_PLL_528_DENOM_B(ACC_SPREAD_SPECTRUM_DENOM),
> + &ccm->analog_pll_528_denom);
> +}
> +
> +/* MMC board initialization is needed till adding DM support in SPL */
> +#if IS_ENABLED(CONFIG_FSL_ESDHC_IMX) && !IS_ENABLED(CONFIG_DM_MMC)
> +#include <mmc.h>
> +#include <fsl_esdhc_imx.h>
> +
> +static const iomux_v3_cfg_t usdhc2_pads[] = {
> + IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(0x00017069)),
> + IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(0x00010038)),
> + IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(0x00017069)),
> + IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(0x00017069)),
> + IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(0x00017069)),
> + IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(0x00017069)),
> + IOMUX_PADS(PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(0x0001B0B0)), /* CD */
> +};
> +
> +static const iomux_v3_cfg_t usdhc4_pads[] = {
> + IOMUX_PADS(PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(0x00017059)),
> + IOMUX_PADS(PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(0x00010059)),
> + IOMUX_PADS(PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(0x00017059)),
> + IOMUX_PADS(PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(0x00017059)),
> + IOMUX_PADS(PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(0x00017059)),
> + IOMUX_PADS(PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(0x00017059)),
> + IOMUX_PADS(PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(0x00017059)),
> + IOMUX_PADS(PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(0x00017059)),
> + IOMUX_PADS(PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(0x00017059)),
> + IOMUX_PADS(PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(0x00017059)),
> +};
> +
> +struct fsl_esdhc_cfg usdhc_cfg[2] = {
> + {USDHC2_BASE_ADDR, 1, 4},
> + {USDHC4_BASE_ADDR, 1, 8},
> +};
> +
> +#define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4)
> +
> +int board_mmc_getcd(struct mmc *mmc)
> +{
> + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
> + int ret = 0;
> +
> + detect_board();
> +
> + switch (cfg->esdhc_base) {
> + case USDHC2_BASE_ADDR:
> + return !gpio_get_value(USDHC2_CD_GPIO);
> + case USDHC4_BASE_ADDR:
> + return 1; /* eMMC always present */
> + }
> +
> + return ret;
> +}
> +
> +int board_mmc_init(struct bd_info *bis)
> +{
> + int i, ret;
> +
> + gpio_direction_input(USDHC2_CD_GPIO);
> + /*
> + * According to the board_mmc_init() the following map is done:
> + * (U-boot device node) (Physical Port)
> + * mmc0 USDHC2
> + * mmc1 USDHC4
> + */
> + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
> + switch (i) {
> + case 0:
> + SETUP_IOMUX_PADS(usdhc2_pads);
> + usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
> + break;
> + case 1:
> + SETUP_IOMUX_PADS(usdhc4_pads);
> + usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
> + break;
> + default:
> + printf("Warning - USDHC%d controller not supporting\n",
> + i + 1);
> + return 0;
> + }
> +
> + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
> + if (ret) {
> + printf("Warning: failed to initialize mmc dev %d\n", i);
> + return ret;
> + }
> + }
> +
> + return 0;
> +}
> +#endif
> +
> +void board_boot_order(u32 *spl_boot_list)
> +{
> + u32 bmode = imx6_src_get_boot_mode();
> + u8 boot_dev = BOOT_DEVICE_MMC1;
> +
> + detect_board();
> +
> + switch ((bmode & IMX6_BMODE_MASK) >> IMX6_BMODE_SHIFT) {
> + case IMX6_BMODE_SD:
> + case IMX6_BMODE_ESD:
> + /* SD/eSD - BOOT_DEVICE_MMC1 */
> + if (IS_ENABLED(CONFIG_SYS_BOOT_EMMC)) {
> + /*
> + * boot from SD is not allowed, if boot from eMMC is
> + * configured.
> + */
> + puts("SD boot not allowed\n");
> + spl_boot_list[0] = BOOT_DEVICE_NONE;
> + return;
> + }
> +
> + boot_dev = BOOT_DEVICE_MMC1;
> + break;
> +
> + case IMX6_BMODE_MMC:
> + case IMX6_BMODE_EMMC:
> + /* MMC/eMMC */
> + boot_dev = BOOT_DEVICE_MMC2;
> + break;
> + default:
> + /* Default - BOOT_DEVICE_MMC1 */
> + printf("Wrong board boot order\n");
> + break;
> + }
> +
> + spl_boot_list[0] = boot_dev;
> +}
> +
> +static void setup_ddr(void)
> +{
> + struct board_info *binfo = detect_board();
> +
> + switch (binfo->rev) {
> + case PFID_REV_20:
> + case PFID_REV_21:
> + case PFID_REV_22:
> + default:
> + /* Rev 2 board has i.MX6 Dual with 64-bit RAM */
> + mx6dq_dram_iocfg(acc_mx6d_mem_ddr3_1066.width,
> + &acc_mx6d_ddr_ioregs,
> + &acc_mx6d_grp_ioregs);
> + mx6_dram_cfg(&acc_mx6d_ddr_info, &acc_mx6d_mmdc_calib,
> + &acc_mx6d_mem_ddr3_1066);
> + /* Perform DDR DRAM calibration */
> + udelay(100);
> + mmdc_do_write_level_calibration(&acc_mx6d_ddr_info);
> + mmdc_do_dqs_calibration(&acc_mx6d_ddr_info);
> + break;
> + }
> +}
> +
> +void board_init_f(ulong dummy)
> +{
> + /* setup AIPS and disable watchdog power-down counter (only enabled after reset) */
> + arch_cpu_init();
> +
> + ccgr_init();
> + gpr_init();
> +
> + /* setup GP timer */
> + timer_init();
> +
> + /* Enable device tree and early DM support*/
> + spl_early_init();
> +
> + /* Setup early required pinmuxes */
> + setup_iomux_early();
> + set_early_gpio();
> +
> + /* Setup UART pinmux */
> + setup_iomux_uart();
> +
> + /* UART clocks enabled and gd valid - init serial console */
> + preloader_console_init();
> +
> + setup_ddr();
> +
> + /* Clear the BSS. */
> + memset(__bss_start, 0, __bss_end - __bss_start);
> +
> + /* load/boot image from boot device */
> + board_init_r(NULL, 0);
> +}
> +#endif
> +
> +#if IS_ENABLED(CONFIG_USB_EHCI_MX6)
> +#define USB_OTHERREGS_OFFSET 0x800
> +#define UCTRL_PWR_POL BIT(9)
> +
> +int board_usb_phy_mode(int port)
> +{
> + if (port == 1)
> + return USB_INIT_HOST;
> + else
> + return usb_phy_mode(port);
> +}
> +
> +int board_ehci_hcd_init(int port)
> +{
> + u32 *usbnc_usb_ctrl;
> +
> + if (port > 1)
> + return -EINVAL;
> +
> + usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
> + port * 4);
> +
> + /* Set Power polarity */
> + setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
> +
> + return 0;
> +}
> +#endif
> +
> +int board_fit_config_name_match(const char *name)
> +{
> + if (!strcmp(name, "imx6q-bosch-acc"))
> + return 0;
> + return -1;
> +}
> +
> +void reset_cpu(ulong addr)
> +{
> + puts("Hanging CPU for watchdog reset!\n");
> + hang();
> +}
> +
> +#if CONFIG_IS_ENABLED(SHOW_BOOT_PROGRESS)
> +void show_boot_progress(int val)
> +{
> + u32 fuseval;
> + int ret;
> +
> + if (val < 0)
> + val *= -1;
> +
> + switch (val) {
> + case BOOTSTAGE_ID_ENTER_CLI_LOOP:
> + printf("autoboot failed, check fuse\n");
> + ret = fuse_read(0, 6, &fuseval);
> + if (ret == 0 && (fuseval & 0x2) == 0x0) {
> + printf("Enter cmdline, as device not closed\n");
> + return;
> + }
> + ret = fuse_read(5, 7, &fuseval);
> + if (ret == 0 && fuseval == 0x0) {
> + printf("Enter cmdline, as it is a Development device\n");
> + return;
> + }
> + panic("do not enter cmdline");
> + break;
> + }
> +}
> +#endif
> diff --git a/configs/imx6q_bosch_acc_defconfig b/configs/imx6q_bosch_acc_defconfig
> new file mode 100644
> index 0000000000..3c02f0f5dd
> --- /dev/null
> +++ b/configs/imx6q_bosch_acc_defconfig
> @@ -0,0 +1,110 @@
> +CONFIG_ARM=y
> +CONFIG_ARCH_MX6=y
> +CONFIG_SYS_TEXT_BASE=0x17780000
> +CONFIG_SYS_MALLOC_LEN=0x01000000
> +CONFIG_SYS_MALLOC_F_LEN=0x9000
> +CONFIG_SPL_GPIO=y
> +CONFIG_SPL_LIBCOMMON_SUPPORT=y
> +CONFIG_SPL_LIBGENERIC_SUPPORT=y
> +CONFIG_NR_DRAM_BANKS=1
> +CONFIG_ENV_SIZE=0x1000
> +CONFIG_ENV_OFFSET=0x1fe000
> +CONFIG_MX6QDL=y
> +CONFIG_MX6_DDRCAL=y
> +CONFIG_TARGET_MX6Q_ACC=y
> +CONFIG_DEFAULT_DEVICE_TREE="imx6q-bosch-acc"
> +CONFIG_SPL_TEXT_BASE=0x00908000
> +CONFIG_SPL_MMC=y
> +CONFIG_SPL_SERIAL=y
> +CONFIG_SPL_DRIVERS_MISC=y
> +CONFIG_BOOTCOUNT_BOOTLIMIT=8
> +CONFIG_SPL_SIZE_LIMIT=69632
> +CONFIG_SPL=y
> +CONFIG_ENV_OFFSET_REDUND=0x1ff000
> +CONFIG_IMX_HAB=y
> +# CONFIG_CMD_BMODE is not set
> +# CONFIG_CMD_DEKBLOB is not set
> +CONFIG_BUILD_TARGET=""
> +# CONFIG_LOCALVERSION_AUTO is not set
> +CONFIG_FIT=y
> +CONFIG_FIT_SIGNATURE=y
> +CONFIG_FIT_VERBOSE=y
> +CONFIG_SHOW_BOOT_PROGRESS=y
> +CONFIG_USE_BOOTCOMMAND=y
> +CONFIG_BOOTCOMMAND="run mmc_mmc_fit"
> +CONFIG_SPL_BOARD_INIT=y
> +CONFIG_SPL_RAW_IMAGE_SUPPORT=y
> +CONFIG_SPL_SEPARATE_BSS=y
> +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xaa
> +# CONFIG_SPL_CRC32 is not set
> +# CONFIG_SPL_CRYPTO is not set
> +CONFIG_SPL_WATCHDOG=y
> +CONFIG_HUSH_PARSER=y
> +# CONFIG_CMD_BDI is not set
> +# CONFIG_CMD_CONSOLE is not set
> +# CONFIG_CMD_BOOTD is not set
> +# CONFIG_CMD_ELF is not set
> +# CONFIG_CMD_FDT is not set
> +# CONFIG_CMD_GO is not set
> +# CONFIG_CMD_IMI is not set
> +# CONFIG_CMD_XIMG is not set
> +# CONFIG_CMD_EXPORTENV is not set
> +# CONFIG_CMD_IMPORTENV is not set
> +# CONFIG_CMD_ENV_EXISTS is not set
> +# CONFIG_CMD_CRC32 is not set
> +# CONFIG_CMD_MEMORY is not set
> +# CONFIG_CMD_FUSE is not set
> +# CONFIG_CMD_LOADB is not set
> +# CONFIG_CMD_LOADS is not set
> +CONFIG_CMD_MMC=y
> +CONFIG_CMD_PART=y
> +# CONFIG_CMD_PINMUX is not set
> +# CONFIG_CMD_ECHO is not set
> +# CONFIG_CMD_ITEST is not set
> +# CONFIG_CMD_SOURCE is not set
> +# CONFIG_CMD_SETEXPR is not set
> +# CONFIG_CMD_NET is not set
> +# CONFIG_CMD_BLOCK_CACHE is not set
> +# CONFIG_CMD_SLEEP is not set
> +# CONFIG_CMD_MP is not set
> +# CONFIG_CMD_HASH is not set
> +CONFIG_CMD_EXT4=y
> +CONFIG_DOS_PARTITION=y
> +CONFIG_EFI_PARTITION=y
> +# CONFIG_SPL_EFI_PARTITION is not set
> +CONFIG_SPL_OF_CONTROL=y
> +CONFIG_MULTI_DTB_FIT=y
> +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clocks clock-names interrupt-parent"
> +CONFIG_ENV_OVERWRITE=y
> +CONFIG_ENV_IS_NOWHERE=y
> +CONFIG_ENV_IS_IN_MMC=y
> +CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
> +CONFIG_SYS_MMC_ENV_PART=1
> +CONFIG_ENV_APPEND=y
> +CONFIG_ENV_WRITEABLE_LIST=y
> +CONFIG_ENV_ACCESS_IGNORE_FORCE=y
> +CONFIG_VERSION_VARIABLE=y
> +CONFIG_TFTP_BLOCKSIZE=512
> +CONFIG_SPL_DM=y
> +CONFIG_BOOTCOUNT_LIMIT=y
> +CONFIG_DM_BOOTCOUNT=y
> +CONFIG_DM_BOOTCOUNT_PMIC_PFUZE100=y
> +CONFIG_SYS_I2C_MXC=y
> +CONFIG_SUPPORT_EMMC_BOOT=y
> +CONFIG_FSL_USDHC=y
> +CONFIG_PHYLIB=y
> +CONFIG_FEC_MXC=y
> +CONFIG_MII=y
> +CONFIG_PINCTRL=y
> +CONFIG_PINCTRL_IMX6=y
> +CONFIG_DM_PMIC=y
> +CONFIG_DM_PMIC_PFUZE100=y
> +CONFIG_DM_SERIAL=y
> +CONFIG_MXC_UART=y
> +CONFIG_WATCHDOG_TIMEOUT_MSECS=60000
> +CONFIG_IMX_WATCHDOG=y
> +CONFIG_WDT=y
> +CONFIG_EXT4_WRITE=y
> +CONFIG_FS_FAT=y
> +CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
> +# CONFIG_EFI_LOADER is not set
> diff --git a/include/configs/imx6q-bosch-acc.h b/include/configs/imx6q-bosch-acc.h
> new file mode 100644
> index 0000000000..686d5f007f
> --- /dev/null
> +++ b/include/configs/imx6q-bosch-acc.h
> @@ -0,0 +1,128 @@
> +/* SPDX-License-Identifier: GPL-2.0+
> + *
> + * Copyright (c) 2017 DENX Software Engineering GmbH, Heiko Schocher <hs at denx.de>
> + * Copyright (c) 2019 Bosch Thermotechnik GmbH
> + * Copyright (c) 2022 DENX Software Engineering GmbH, Philip Oberfichtner <pro at denx.de>
> + */
> +
> +#ifndef __IMX6Q_ACC_H
> +#define __IMX6Q_ACC_H
> +
> +#include <linux/sizes.h>
> +#include "mx6_common.h"
> +
> +#ifdef CONFIG_SYS_BOOT_EMMC
> +#define MMC_ROOTFS_DEV 0
> +#define MMC_ROOTFS_PART 2
> +#endif
> +
> +#ifdef CONFIG_SYS_BOOT_EMMC
> +/* eMMC Boot */
> +#define ENV_EXTRA \
> + "mmcdev=" __stringify(MMC_ROOTFS_DEV) "\0" \
> + "mmcpart=" __stringify(MMC_ROOTFS_PART) "\0" \
> + "fitpart=1\0" \
> + "optargs=ro quiet systemd.gpt_auto=false\0" \
> + "production=1\0" \
> + "mmcautodetect=yes\0" \
> + "mmcrootfstype=ext4\0" \
> + "finduuid=part uuid mmc ${mmcdev}:${mmcpart} uuid\0" \
> + "mmcargs=run finduuid; setenv bootargs " \
> + "root=PARTUUID=${uuid} ${optargs} rootfstype=${mmcrootfstype}\0" \
> + "mmc_mmc_fit=run env_persist; run setbm; run mmcloadfit; " \
> + "run auth_fit_or_reset; run mmcargs addcon; " \
> + "bootm ${fit_addr}#${bootconf}\0" \
> + "bootset=0\0" \
> + "setbm=if test ${bootset} -eq 1; " \
> + "then setenv mmcpart 4; setenv fitpart 3; " \
> + "else; setenv mmcpart 2; setenv fitpart 1; fi\0" \
> + "handle_ustate=if test ${ustate} -eq 2; then setenv ustate 3; fi\0" \
> + "switch_bootset=if test ${bootset} -eq 1; then setenv bootset 0; " \
> + "else; setenv bootset 1;fi\0" \
> + "env_persisted=0\0" \
> + "env_persist=if test ${env_persisted} != 1; " \
> + "then env set env_persisted 1; run save_env; fi;\0" \
> + "save_env=env save; env save\0" \
> + "altbootcmd=run handle_ustate; run switch_bootset; run save_env; run bootcmd\0"
> +
> +#define CONFIG_ENV_FLAGS_LIST_STATIC \
> + "bootset:bw," \
> + "clone_pending:bw," \
> + "endurance_test:bw," \
> + "env_persisted:bw," \
> + "factory_reset:bw," \
> + "fdtcontroladdr:xw," \
> + "fitpart:dw," \
> + "mmcpart:dw," \
> + "production:bw," \
> + "ustate:dw"
> +
> +#else
> +/* SD Card boot */
> +#define ENV_EXTRA \
> + "mmcdev=1\0" \
> + "fitpart=1\0" \
> + "rootpart=2\0" \
> + "optargs=ro systemd.gpt_auto=false\0" \
> + "finduuid=part uuid mmc ${mmcdev}:${rootpart} uuid\0" \
> + "mmcargs=run finduuid;setenv bootargs root=PARTUUID=${uuid} ${optargs}\0" \
> + "mmc_mmc_fit=run mmcloadfit; run auth_fit_or_reset; run mmcargs addcon; " \
> + "bootm ${fit_addr}#${bootconf}\0"
> +
> +#endif
> +
> +/* Default environment */
> +#define CONFIG_EXTRA_ENV_SETTINGS \
> + "bootconf=conf-imx6q-bosch-acc.dtb\0"\
> + "mmcfit_name=fitImage\0" \
> + "mmcloadfit=ext4load mmc ${mmcdev}:${fitpart} ${fit_addr} ${mmcfit_name}\0" \
> + "auth_fit_or_reset=hab_auth_img ${fit_addr} ${filesize} || reset\0" \
> + "console=ttymxc0\0" \
> + "addcon=setenv bootargs ${bootargs} console=${console},${baudrate}\0" \
> + "fit_addr=19000000\0" \
> + ENV_EXTRA
> +
> +/* Physical Memory Map */
> +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
> +
> +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
> +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
> +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
> +
> +#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
> +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
> +
> +/* Ethernet */
> +#ifdef CONFIG_FEC_MXC
> +#define CONFIG_FEC_MXC_PHYADDR 0
> +#define CONFIG_FEC_XCV_TYPE RMII
Reason is this one.
I wonder myself why this is required - I set this a lot of time *before*
the switch to DM, but then the connection type is set in DT and this is
not required anymore. Are you sure you need it ?
Regards,
Stefano
> +#endif
> +
> +/* SPL */
> +#ifdef CONFIG_SPL
> +#include "imx6_spl.h"
> +
> +#ifdef CONFIG_SPL_BUILD
> +#define CONFIG_SYS_FSL_USDHC_NUM 2
> +
> +#ifdef CONFIG_SYS_BOOT_EMMC
> +
> +/* Boot from eMMC */
> +#define CONFIG_SYS_FSL_ESDHC_ADDR 1
> +
> +#else
> +
> +/* Boot from SD-card */
> +# define CONFIG_SYS_FSL_ESDHC_ADDR 0
> +
> +#endif
> +
> +#endif
> +#endif
> +
> +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
> +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
> +#define CONFIG_MXC_USB_FLAGS 0
> +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 /* Enabled USB controller number */
> +
> +#endif /* __IMX6Q_ACC_H */
--
=====================================================================
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
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