[PATCH 01/31] arm: mediatek: add support for MediaTek MT7986 SoC
Weijie Gao
weijie.gao at mediatek.com
Thu Aug 4 05:34:28 CEST 2022
This patch adds basic support for MediaTek MT7986 SoC.
This include the file that will initialize the SoC after boot and its
device tree.
Signed-off-by: Weijie Gao <weijie.gao at mediatek.com>
---
arch/arm/dts/mt7986-u-boot.dtsi | 33 ++
arch/arm/dts/mt7986.dtsi | 341 ++++++++++++++++++
arch/arm/mach-mediatek/Kconfig | 11 +
arch/arm/mach-mediatek/Makefile | 1 +
arch/arm/mach-mediatek/mt7986/Makefile | 4 +
arch/arm/mach-mediatek/mt7986/init.c | 53 +++
arch/arm/mach-mediatek/mt7986/lowlevel_init.S | 30 ++
7 files changed, 473 insertions(+)
create mode 100644 arch/arm/dts/mt7986-u-boot.dtsi
create mode 100644 arch/arm/dts/mt7986.dtsi
create mode 100644 arch/arm/mach-mediatek/mt7986/Makefile
create mode 100644 arch/arm/mach-mediatek/mt7986/init.c
create mode 100644 arch/arm/mach-mediatek/mt7986/lowlevel_init.S
diff --git a/arch/arm/dts/mt7986-u-boot.dtsi
b/arch/arm/dts/mt7986-u-boot.dtsi
new file mode 100644
index 0000000000..95671f8afa
--- /dev/null
+++ b/arch/arm/dts/mt7986-u-boot.dtsi
@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2022 MediaTek Inc.
+ * Author: Sam Shih <sam.shih at mediatek.com>
+ */
+
+&topckgen {
+ u-boot,dm-pre-reloc;
+};
+
+&pericfg {
+ u-boot,dm-pre-reloc;
+};
+
+&apmixedsys {
+ u-boot,dm-pre-reloc;
+};
+
+&timer0 {
+ u-boot,dm-pre-reloc;
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+};
+
+&snand {
+ u-boot,dm-pre-reloc;
+};
+
+&pinctrl {
+ u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/mt7986.dtsi b/arch/arm/dts/mt7986.dtsi
new file mode 100644
index 0000000000..f235bd8b8c
--- /dev/null
+++ b/arch/arm/dts/mt7986.dtsi
@@ -0,0 +1,341 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2022 MediaTek Inc.
+ * Author: Sam Shih <sam.shih at mediatek.com>
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/phy/phy.h>
+#include <dt-bindings/clock/mt7986-clk.h>
+#include <dt-bindings/reset/mt7629-reset.h>
+#include <dt-bindings/pinctrl/mt65xx.h>
+
+/ {
+ compatible = "mediatek,mt7986";
+ interrupt-parent = <&gic>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ config {
+ u-boot,mmc-env-partition = "u-boot-env";
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cpu0: cpu at 0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0>;
+ };
+ cpu1: cpu at 1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x1>;
+ };
+ cpu2: cpu at 2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x1>;
+ };
+ cpu3: cpu at 3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x1>;
+ };
+ };
+
+ dummy_clk: dummy12m {
+ compatible = "fixed-clock";
+ clock-frequency = <12000000>;
+ #clock-cells = <0>;
+ /* must need this line, or uart uanable to get dummy_clk */
+ u-boot,dm-pre-reloc;
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupt-parent = <&gic>;
+ clock-frequency = <13000000>;
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+ arm,cpu-registers-not-fw-configured;
+ };
+
+ timer0: timer at 10008000 {
+ compatible = "mediatek,mt7986-timer";
+ reg = <0x10008000 0x1000>;
+ interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&infracfg CK_INFRA_CK_F26M>;
+ clock-names = "gpt-clk";
+ u-boot,dm-pre-reloc;
+ };
+
+ watchdog: watchdog at 1001c000 {
+ compatible = "mediatek,mt7986-wdt";
+ reg = <0x1001c000 0x1000>;
+ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+ #reset-cells = <1>;
+ status = "disabled";
+ };
+
+ gic: interrupt-controller at c000000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <3>;
+ interrupt-parent = <&gic>;
+ interrupt-controller;
+ reg = <0x0c000000 0x40000>, /* GICD */
+ <0x0c080000 0x200000>; /* GICR */
+
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ fixed_plls: apmixedsys at 1001E000 {
+ compatible = "mediatek,mt7986-fixed-plls";
+ reg = <0x1001E000 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ topckgen: topckgen at 1001B000 {
+ compatible = "mediatek,mt7986-topckgen";
+ reg = <0x1001B000 0x1000>;
+ clock-parent = <&fixed_plls>;
+ #clock-cells = <1>;
+ };
+
+ infracfg_ao: infracfg_ao at 10001000 {
+ compatible = "mediatek,mt7986-infracfg_ao";
+ reg = <0x10001000 0x68>;
+ clock-parent = <&infracfg>;
+ #clock-cells = <1>;
+ };
+
+ infracfg: infracfg at 10001040 {
+ compatible = "mediatek,mt7986-infracfg";
+ reg = <0x10001000 0x1000>;
+ clock-parent = <&topckgen>;
+ #clock-cells = <1>;
+ };
+
+ pinctrl: pinctrl at 1001f000 {
+ compatible = "mediatek,mt7986-pinctrl";
+ reg = <0x1001f000 0x1000>,
+ <0x11c30000 0x1000>,
+ <0x11c40000 0x1000>,
+ <0x11e20000 0x1000>,
+ <0x11e30000 0x1000>,
+ <0x11f00000 0x1000>,
+ <0x11f10000 0x1000>,
+ <0x1000b000 0x1000>;
+ reg-names = "gpio_base", "iocfg_rt_base", "iocfg_rb_base",
+ "iocfg_lt_base", "iocfg_lb_base", "iocfg_tr_base",
+ "iocfg_tl_base", "eint";
+ gpio: gpio-controller {
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+ };
+
+ pwm: pwm at 10048000 {
+ compatible = "mediatek,mt7986-pwm";
+ reg = <0x10048000 0x1000>;
+ #clock-cells = <1>;
+ #pwm-cells = <2>;
+ interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&infracfg CK_INFRA_PWM>,
+ <&infracfg_ao CK_INFRA_PWM_BSEL>,
+ <&infracfg_ao CK_INFRA_PWM1_CK>,
+ <&infracfg_ao CK_INFRA_PWM2_CK>;
+ assigned-clocks = <&topckgen CK_TOP_PWM_SEL>,
+ <&infracfg CK_INFRA_PWM_BSEL>,
+ <&infracfg CK_INFRA_PWM1_SEL>,
+ <&infracfg CK_INFRA_PWM2_SEL>;
+ assigned-clock-parents = <&topckgen CK_TOP_CB_M_D4>,
+ <&infracfg CK_INFRA_PWM>,
+ <&infracfg CK_INFRA_PWM>,
+ <&infracfg CK_INFRA_PWM>;
+ clock-names = "top", "main", "pwm1", "pwm2";
+ status = "disabled";
+ u-boot,dm-pre-reloc;
+ };
+
+ uart0: serial at 11002000 {
+ compatible = "mediatek,hsuart";
+ reg = <0x11002000 0x400>;
+ interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&infracfg_ao CK_INFRA_UART0_CK>;
+ assigned-clocks = <&topckgen CK_TOP_UART_SEL>,
+ <&infracfg_ao CK_INFRA_UART0_SEL>;
+ assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>,
+ <&infracfg CK_INFRA_UART>;
+ mediatek,force-highspeed;
+ status = "disabled";
+ u-boot,dm-pre-reloc;
+ };
+
+ uart1: serial at 11003000 {
+ compatible = "mediatek,hsuart";
+ reg = <0x11003000 0x400>;
+ interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&infracfg_ao CK_INFRA_UART1_CK>;
+ assigned-clocks = <&infracfg CK_INFRA_UART1_SEL>;
+ assigned-clock-parents = <&infracfg CK_INFRA_CK_F26M>;
+ mediatek,force-highspeed;
+ status = "disabled";
+ };
+
+ uart2: serial at 11004000 {
+ compatible = "mediatek,hsuart";
+ reg = <0x11004000 0x400>;
+ interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&infracfg_ao CK_INFRA_UART2_CK>;
+ assigned-clocks = <&infracfg CK_INFRA_UART2_SEL>;
+ assigned-clock-parents = <&infracfg CK_INFRA_CK_F26M>;
+ mediatek,force-highspeed;
+ status = "disabled";
+ };
+
+ snand: snand at 11005000 {
+ compatible = "mediatek,mt7986-snand";
+ reg = <0x11005000 0x1000>,
+ <0x11006000 0x1000>;
+ reg-names = "nfi", "ecc";
+ clocks = <&infracfg_ao CK_INFRA_SPINFI1_CK>,
+ <&infracfg_ao CK_INFRA_NFI1_CK>,
+ <&infracfg_ao CK_INFRA_NFI_HCK_CK>;
+ clock-names = "pad_clk", "nfi_clk", "nfi_hclk";
+ assigned-clocks = <&topckgen CK_TOP_SPINFI_SEL>,
+ <&topckgen CK_TOP_NFI1X_SEL>;
+ assigned-clock-parents = <&topckgen CK_TOP_CB_M_D8>,
+ <&topckgen CK_TOP_CB_M_D8>;
+ status = "disabled";
+ };
+
+ ethsys: syscon at 15000000 {
+ compatible = "mediatek,mt7986-ethsys", "syscon";
+ reg = <0x15000000 0x1000>;
+ clock-parent = <&topckgen>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ eth: ethernet at 15100000 {
+ compatible = "mediatek,mt7986-eth", "syscon";
+ reg = <0x15100000 0x20000>;
+ resets = <ðsys ETHSYS_FE_RST>;
+ reset-names = "fe";
+ mediatek,ethsys = <ðsys>;
+ mediatek,sgmiisys = <&sgmiisys0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ sgmiisys0: syscon at 10060000 {
+ compatible = "mediatek,mt7986-sgmiisys", "syscon";
+ reg = <0x10060000 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ sgmiisys1: syscon at 10070000 {
+ compatible = "mediatek,mt7986-sgmiisys", "syscon";
+ reg = <0x10070000 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ spi0: spi at 1100a000 {
+ compatible = "mediatek,ipm-spi";
+ reg = <0x1100a000 0x100>;
+ clocks = <&infracfg_ao CK_INFRA_SPI0_CK>,
+ <&topckgen CK_TOP_SPI_SEL>;
+ assigned-clocks = <&topckgen CK_TOP_SPI_SEL>,
+ <&infracfg CK_INFRA_SPI0_SEL>;
+ assigned-clock-parents = <&topckgen CK_TOP_CB_M_D2>,
+ <&topckgen CK_INFRA_ISPI0>;
+ clock-names = "sel-clk", "spi-clk";
+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ spi1: spi at 1100b000 {
+ compatible = "mediatek,ipm-spi";
+ reg = <0x1100b000 0x100>;
+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ mmc0: mmc at 11230000 {
+ compatible = "mediatek,mt7986-mmc";
+ reg = <0x11230000 0x1000>,
+ <0x11C20000 0x1000>;
+ interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&topckgen CK_TOP_EMMC_416M>,
+ <&topckgen CK_TOP_EMMC_250M>,
+ <&infracfg_ao CK_INFRA_MSDC_CK>;
+ assigned-clocks = <&topckgen CK_TOP_EMMC_416M_SEL>,
+ <&topckgen CK_TOP_EMMC_250M_SEL>;
+ assigned-clock-parents = <&topckgen CK_TOP_CB_M_416M>,
+ <&topckgen CK_TOP_NET1_D5_D2>;
+ clock-names = "source", "hclk", "source_cg";
+ status = "disabled";
+ };
+
+ xhci: xhci at 11200000 {
+ compatible = "mediatek,mt7986-xhci",
+ "mediatek,mtk-xhci";
+ reg = <0x11200000 0x2e00>,
+ <0x11203e00 0x0100>;
+ reg-names = "mac", "ippc";
+ interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&u2port0 PHY_TYPE_USB2>,
+ <&u3port0 PHY_TYPE_USB3>,
+ <&u2port1 PHY_TYPE_USB2>;
+ clocks = <&dummy_clk>,
+ <&dummy_clk>,
+ <&dummy_clk>,
+ <&dummy_clk>,
+ <&dummy_clk>;
+ clock-names = "sys_ck",
+ "xhci_ck",
+ "ref_ck",
+ "mcu_ck",
+ "dma_ck";
+ tpl-support;
+ status = "okay";
+ };
+
+ usbtphy: usb-phy at 11e10000 {
+ compatible = "mediatek,mt7986",
+ "mediatek,generic-tphy-v2";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ status = "okay";
+
+ u2port0: usb-phy at 11e10000 {
+ reg = <0x11e10000 0x700>;
+ clocks = <&dummy_clk>;
+ clock-names = "ref";
+ #phy-cells = <1>;
+ status = "okay";
+ };
+
+ u3port0: usb-phy at 11e10700 {
+ reg = <0x11e10700 0x900>;
+ clocks = <&dummy_clk>;
+ clock-names = "ref";
+ #phy-cells = <1>;
+ status = "okay";
+ };
+
+ u2port1: usb-phy at 11e11000 {
+ reg = <0x11e11000 0x700>;
+ clocks = <&dummy_clk>;
+ clock-names = "ref";
+ #phy-cells = <1>;
+ status = "okay";
+ };
+ };
+};
diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-mediatek/Kconfig
index f79a5c62cd..e059a013db 100644
--- a/arch/arm/mach-mediatek/Kconfig
+++ b/arch/arm/mach-mediatek/Kconfig
@@ -40,6 +40,14 @@ config TARGET_MT7629
including DDR3, crypto engine, 3x3 11n/ac Wi-Fi, Gigabit Ethernet,
switch, USB3.0, PCIe, UART, SPI, I2C and PWM.
+config TARGET_MT7986
+ bool "MediaTek MT7986 SoC"
+ select ARM64
+ help
+ The MediaTek MT7986 is a ARM64-based SoC with a quad-core Cortex-A53.
+ including UART, SPI, SPI flash, USB3.0, MMC, NAND, SNFI, PWM, PCIe,
+ Gigabit Ethernet, I2C, built-in 4x4 Wi-Fi, and PCIe.
+
config TARGET_MT8183
bool "MediaTek MT8183 SoC"
select ARM64
@@ -84,6 +92,7 @@ config SYS_BOARD
default "mt7622" if TARGET_MT7622
default "mt7623" if TARGET_MT7623
default "mt7629" if TARGET_MT7629
+ default "mt7986" if TARGET_MT7986
default "mt8183" if TARGET_MT8183
default "mt8512" if TARGET_MT8512
default "mt8516" if TARGET_MT8516
@@ -99,6 +108,7 @@ config SYS_CONFIG_NAME
default "mt7622" if TARGET_MT7622
default "mt7623" if TARGET_MT7623
default "mt7629" if TARGET_MT7629
+ default "mt7986" if TARGET_MT7986
default "mt8183" if TARGET_MT8183
default "mt8512" if TARGET_MT8512
default "mt8516" if TARGET_MT8516
@@ -113,6 +123,7 @@ config MTK_BROM_HEADER_INFO
string
default "media=nor" if TARGET_MT8518 || TARGET_MT8512 || TARGET_MT7629 ||
TARGET_MT7622
default "media=emmc" if TARGET_MT8516 || TARGET_MT8365 || TARGET_MT8183
+ default "media=snand;nandinfo=2k+64" if TARGET_MT7986
default "lk=1" if TARGET_MT7623
endif
diff --git a/arch/arm/mach-mediatek/Makefile
b/arch/arm/mach-mediatek/Makefile
index 0f5b0c16d2..fe5c3a837c 100644
--- a/arch/arm/mach-mediatek/Makefile
+++ b/arch/arm/mach-mediatek/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_MT8512) += mt8512/
obj-$(CONFIG_TARGET_MT7622) += mt7622/
obj-$(CONFIG_TARGET_MT7623) += mt7623/
obj-$(CONFIG_TARGET_MT7629) += mt7629/
+obj-$(CONFIG_TARGET_MT7986) += mt7986/
obj-$(CONFIG_TARGET_MT8183) += mt8183/
obj-$(CONFIG_TARGET_MT8516) += mt8516/
obj-$(CONFIG_TARGET_MT8518) += mt8518/
diff --git a/arch/arm/mach-mediatek/mt7986/Makefile
b/arch/arm/mach-mediatek/mt7986/Makefile
new file mode 100644
index 0000000000..007eb4a367
--- /dev/null
+++ b/arch/arm/mach-mediatek/mt7986/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0
+
+obj-y += init.o
+obj-y += lowlevel_init.o
diff --git a/arch/arm/mach-mediatek/mt7986/init.c
b/arch/arm/mach-mediatek/mt7986/init.c
new file mode 100644
index 0000000000..4884cbdc67
--- /dev/null
+++ b/arch/arm/mach-mediatek/mt7986/init.c
@@ -0,0 +1,53 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2022 MediaTek Inc.
+ * Author: Sam Shih <sam.shih at mediatek.com>
+ */
+
+#include <fdtdec.h>
+#include <asm/armv8/mmu.h>
+#include <init.h>
+#include <asm/system.h>
+#include <asm/global_data.h>
+#include <linux/sizes.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int print_cpuinfo(void)
+{
+ printf("CPU: MediaTek MT7986\n");
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, SZ_2G);
+
+ return 0;
+}
+
+void reset_cpu(ulong addr)
+{
+ psci_system_reset();
+}
+
+static struct mm_region mt7986_mem_map[] = {
+ {
+ /* DDR */
+ .virt = 0x40000000UL,
+ .phys = 0x40000000UL,
+ .size = 0x80000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE,
+ }, {
+ .virt = 0x00000000UL,
+ .phys = 0x00000000UL,
+ .size = 0x40000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ 0,
+ }
+};
+
+struct mm_region *mem_map = mt7986_mem_map;
diff --git a/arch/arm/mach-mediatek/mt7986/lowlevel_init.S
b/arch/arm/mach-mediatek/mt7986/lowlevel_init.S
new file mode 100644
index 0000000000..244d2c1385
--- /dev/null
+++ b/arch/arm/mach-mediatek/mt7986/lowlevel_init.S
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2022 MediaTek Inc.
+ * Author: Sam Shih <sam.shih at mediatek.com>
+ */
+
+/*
+ * Switch from AArch64 EL2 to AArch32 EL2
+ * @param inputs:
+ * x0: argument, zero
+ * x1: machine nr
+ * x2: fdt address
+ * x3: input argument
+ * x4: kernel entry point
+ * @param outputs for secure firmware:
+ * x0: function id
+ * x1: kernel entry point
+ * x2: machine nr
+ * x3: fdt address
+*/
+
+.global armv8_el2_to_aarch32
+armv8_el2_to_aarch32:
+ mov x3, x2
+ mov x2, x1
+ mov x1, x4
+ mov x4, #0
+ ldr x0, =0x82000200
+ SMC #0
+ ret
--
2.17.1
More information about the U-Boot
mailing list