[SPAM] rk3399 TPL memory setup code triggers clock frequency limit assertion

[Xavier Drudis Ferran]

El Mon, Aug 08, 2022 at 11:22:49PM +0530, Jagan Teki deia:
> 
> If I remember correctly when I work with YouMin on LPDDR4 the initial
> code to start to check with was 50MHz (It was not working at that time
> with 48MHz). Not sure what to make other changes to fix that to try on
> 48MHz.
> 

Not sure I understand.

Do you mean when you and YouMin worked in this (thanks for your work) 
you had mesured that the code gave 50MHz ? Maybe. It seems out of spec, so it
doesn't have to give 48MHz, I guess it can give whatever. 48MHz is the concluion
of a theory for which we haven't satisfied the hypothesis.

Or do you mean the code for this clock was different when you worked initially,
and that code gave 50MHz theoretically ? I haven't looked at the git log.

> Better resend the patch again and add YouMin and others to see for comments.
> 

I don't have much time right now to pull, see if it applies still and
test again.  Michal just tried, not sure how clean it might have been
for him, or what base he used, so anyone feel free to resend if you
think it's useful or know better who to put in cc. Who would "others" be ?
If I got my Cc: wrong the first time I fear I'll fail again. Michal
just sent a tested-by to my orignal patch[1]. Should a resend fare
better ? Or how many resends?  I may resend this one line patch when I
have time if nobody has resent yet or merged the original.

YouMin helped me confirm and said something unconclusive in private,
not opposing to change it.

[1] https://patchwork.ozlabs.org/project/uboot/patch/20220716103144.GA2167@begut/