[PATCH 3/5] arm: dts: socfpga: Copy existing FW & SEC config to DTS
Jit Loon Lim
jit.loon.lim at intel.com
Mon Dec 5 14:42:17 CET 2022
From: Tien Fong Chee <tien.fong.chee at intel.com>
Copy existing firewall and secure register settings in source codes to
device tree.
Signed-off-by: Tien Fong Chee <tien.fong.chee at intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim at intel.com>
---
arch/arm/dts/socfpga_agilex-u-boot.dtsi | 13 ++-
arch/arm/dts/socfpga_n5x-u-boot.dtsi | 10 ++
arch/arm/dts/socfpga_soc64_u-boot.dtsi | 112 +++++++++++++++++++++
arch/arm/dts/socfpga_stratix10-u-boot.dtsi | 17 +++-
4 files changed, 150 insertions(+), 2 deletions(-)
create mode 100644 arch/arm/dts/socfpga_soc64_u-boot.dtsi
diff --git a/arch/arm/dts/socfpga_agilex-u-boot.dtsi b/arch/arm/dts/socfpga_agilex-u-boot.dtsi
index 08f7cf7f7a..774cebd30c 100644
--- a/arch/arm/dts/socfpga_agilex-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_agilex-u-boot.dtsi
@@ -2,9 +2,10 @@
/*
* U-Boot additions
*
- * Copyright (C) 2019-2020 Intel Corporation <www.intel.com>
+ * Copyright (C) 2019-2021 Intel Corporation <www.intel.com>
*/
+#include "socfpga_soc64_u-boot.dtsi"
#include "socfpga_soc64_fit-u-boot.dtsi"
/{
@@ -84,6 +85,16 @@
u-boot,dm-pre-reloc;
};
+&socfpga_secreg {
+ soc_noc_fw_mpfe_csr_inst_0_mpfe_scr at f8020000 {
+ reg = <0xf8020000 0x0000001c>;
+ intel,offset-settings =
+ <0x00000000 0x00010101>,
+ <0x00000004 0x00000001>;
+ u-boot,dm-pre-reloc;
+ };
+};
+
&sysmgr {
compatible = "altr,sys-mgr", "syscon";
u-boot,dm-pre-reloc;
diff --git a/arch/arm/dts/socfpga_n5x-u-boot.dtsi b/arch/arm/dts/socfpga_n5x-u-boot.dtsi
index d377ae5f69..98cbd4c808 100644
--- a/arch/arm/dts/socfpga_n5x-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_n5x-u-boot.dtsi
@@ -5,6 +5,7 @@
* Copyright (C) 2020-2021 Intel Corporation <www.intel.com>
*/
+#include "socfpga_soc64_u-boot.dtsi"
#include "socfpga_soc64_fit-u-boot.dtsi"
#include <dt-bindings/clock/n5x-clock.h>
@@ -130,6 +131,15 @@
&spi1 {
clocks = <&clkmgr N5X_L4_MAIN_CLK>;
+
+&socfpga_secreg {
+ soc_noc_fw_mpfe_csr_inst_0_mpfe_scr at f8020000 {
+ reg = <0xf8020000 0x0000001c>;
+ intel,offset-settings =
+ <0x00000000 0x00010101>,
+ <0x00000004 0x00000001>;
+ u-boot,dm-pre-reloc;
+ };
};
&sysmgr {
diff --git a/arch/arm/dts/socfpga_soc64_u-boot.dtsi b/arch/arm/dts/socfpga_soc64_u-boot.dtsi
new file mode 100644
index 0000000000..34997b4c30
--- /dev/null
+++ b/arch/arm/dts/socfpga_soc64_u-boot.dtsi
@@ -0,0 +1,112 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * U-Boot additions
+ *
+ * Copyright (C) 2021 Intel Corporation <www.intel.com>
+ */
+
+/ {
+ soc {
+ socfpga_secreg: socfpga-secreg {
+ compatible = "intel,socfpga-secreg";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ u-boot,dm-pre-reloc;
+
+ i_sys_mgr_core at ffd12000 {
+ reg = <0xffd12000 0x00000230>;
+ intel,offset-settings =
+ <0x00000020 0xff010000>,
+ <0x00000024 0xffffffff>;
+ u-boot,dm-pre-reloc;
+ };
+
+ noc_fw_l4_per_l4_per_scr at ffd21000 {
+ reg = <0xffd21000 0x00000074>;
+ intel,offset-settings =
+ <0x00000000 0x01010001>,
+ <0x00000004 0x01010001>,
+ <0x0000000c 0x01010001>,
+ <0x00000010 0x01010001>,
+ <0x0000001c 0x01010001>,
+ <0x00000020 0x01010001>,
+ <0x00000024 0x01010001>,
+ <0x00000028 0x01010001>,
+ <0x0000002c 0x01010001>,
+ <0x00000030 0x01010001>,
+ <0x00000034 0x01010001>,
+ <0x00000040 0x01010001>,
+ <0x00000044 0x01010001>,
+ <0x00000048 0x01010001>,
+ <0x00000050 0x01010001>,
+ <0x00000054 0x01010001>,
+ <0x00000058 0x01010001>,
+ <0x0000005c 0x01010001>,
+ <0x00000060 0x01010001>,
+ <0x00000064 0x01010001>,
+ <0x00000068 0x01010001>,
+ <0x0000006c 0x01010001>,
+ <0x00000070 0x01010001>;
+ u-boot,dm-pre-reloc;
+ };
+
+ noc_fw_l4_sys_l4_sys_scr at ffd21100 {
+ reg = <0xffd21100 0x00000098>;
+ intel,offset-settings =
+ <0x00000008 0x01010001>,
+ <0x0000000c 0x01010001>,
+ <0x00000010 0x01010001>,
+ <0x00000014 0x01010001>,
+ <0x00000018 0x01010001>,
+ <0x0000001c 0x01010001>,
+ <0x00000020 0x01010001>,
+ <0x0000002c 0x01010001>,
+ <0x00000030 0x01010001>,
+ <0x00000034 0x01010001>,
+ <0x00000038 0x01010001>,
+ <0x00000040 0x01010001>,
+ <0x00000044 0x01010001>,
+ <0x00000048 0x01010001>,
+ <0x0000004c 0x01010001>,
+ <0x00000054 0x01010001>,
+ <0x00000058 0x01010001>,
+ <0x0000005c 0x01010001>,
+ <0x00000060 0x01010001>,
+ <0x00000064 0x01010001>,
+ <0x00000068 0x01010001>,
+ <0x0000006c 0x01010001>,
+ <0x00000070 0x01010001>,
+ <0x00000074 0x01010001>,
+ <0x00000078 0x01010001>,
+ <0x00000090 0x01010001>,
+ <0x00000094 0x01010001>;
+ u-boot,dm-pre-reloc;
+ };
+
+ noc_fw_soc2fpga_soc2fpga_scr at ffd21200 {
+ reg = <0xffd21200 0x00000004>;
+ intel,offset-settings = <0x00000000 0x0ffe0101>;
+ u-boot,dm-pre-reloc;
+ };
+
+ noc_fw_lwsoc2fpga_lwsoc2fpga_scr at ffd21300 {
+ reg = <0xffd21300 0x00000004>;
+ intel,offset-settings = <0x00000000 0x0ffe0101>;
+ u-boot,dm-pre-reloc;
+ };
+
+ noc_fw_tcu_tcu_scr at ffd21400 {
+ reg = <0xffd21400 0x00000004>;
+ intel,offset-settings = <0x00000000 0x01010001>;
+ u-boot,dm-pre-reloc;
+ };
+
+ noc_fw_priv_MemoryMap_priv at ffd24800 {
+ reg = <0xffd24800 0x0000000c>;
+ intel,offset-settings =
+ <0x00000000 0xfff73ffb>;
+ u-boot,dm-pre-reloc;
+ };
+ };
+ };
+};
diff --git a/arch/arm/dts/socfpga_stratix10-u-boot.dtsi b/arch/arm/dts/socfpga_stratix10-u-boot.dtsi
index 3e3a378046..577cbf9770 100644
--- a/arch/arm/dts/socfpga_stratix10-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_stratix10-u-boot.dtsi
@@ -2,7 +2,22 @@
/*
* U-Boot additions
*
- * Copyright (C) 2020 Intel Corporation <www.intel.com>
+ * Copyright (C) 2020-2021 Intel Corporation <www.intel.com>
*/
+#include "socfpga_soc64_u-boot.dtsi"
#include "socfpga_soc64_fit-u-boot.dtsi"
+
+&socfpga_secreg {
+ i_ccu_noc_registers at f7000000 {
+ reg = <0xf7000000 0x00049e60>;
+ intel,offset-settings =
+ <0x000105a0 0x00000000>,
+ <0x000105c0 0x00000000>,
+ <0x000105e0 0x00000000>,
+ <0x00010600 0x00000000>,
+ <0x00010620 0x00000000>,
+ <0x00010640 0x00000000>;
+ u-boot,dm-pre-reloc;
+ };
+};
--
2.26.2
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