[PATCH 5/5] arm: socfpga: Switch FW settings from codes to DTS
Jit Loon Lim
jit.loon.lim at intel.com
Mon Dec 5 14:42:19 CET 2022
From: Tien Fong Chee <tien.fong.chee at intel.com>
Switching the firewall, and high privilege registers setting in source
codes over to device tree implementation.
Signed-off-by: Tien Fong Chee <tien.fong.chee at intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim at intel.com>
---
arch/arm/Kconfig | 2 ++
arch/arm/mach-socfpga/Makefile | 29 +++++++++++++------
.../include/mach/system_manager_soc64.h | 3 ++
arch/arm/mach-socfpga/spl_agilex.c | 9 ++++--
arch/arm/mach-socfpga/spl_n5x.c | 8 +++--
arch/arm/mach-socfpga/spl_s10.c | 11 ++++---
configs/socfpga_agilex_nand_atf_defconfig | 1 -
configs/socfpga_agilex_nand_defconfig | 1 -
configs/socfpga_n5x_atf_defconfig | 1 -
configs/socfpga_n5x_defconfig | 1 -
configs/socfpga_n5x_vab_defconfig | 1 -
configs/socfpga_stratix10_nand_atf_defconfig | 1 -
...onfig => socfpga_stratix10_nand_defconfig} | 18 ++++++------
13 files changed, 54 insertions(+), 32 deletions(-)
copy configs/{socfpga_agilex_nand_defconfig => socfpga_stratix10_nand_defconfig} (82%)
mode change 100755 => 100644
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 949ebb46ba..128039e207 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1115,6 +1115,8 @@ config ARCH_SOCFPGA
select SPL_LIBGENERIC_SUPPORT
select SPL_OF_CONTROL
select SPL_SEPARATE_BSS if TARGET_SOCFPGA_SOC64
+ select SPL_DRIVERS_MISC if TARGET_SOCFPGA_SOC64
+ select SPL_SOCFPGA_SEC_REG if TARGET_SOCFPGA_SOC64
select SPL_SERIAL
select SPL_SYSRESET
select SPL_WATCHDOG
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 58a486f6de..0112555926 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -35,10 +35,18 @@ obj-y += mailbox_s10.o
obj-y += misc_soc64.o
obj-y += mmu-arm64_s10.o
obj-y += reset_manager_s10.o
+obj-y += smmu_s10.o
obj-y += system_manager_soc64.o
obj-y += timer_s10.o
obj-y += wrap_handoff_soc64.o
obj-y += wrap_pll_config_soc64.o
+ifndef CONFIG_SPL_BUILD
+obj-$(CONFIG_ARMV8_PSCI) += psci.o
+obj-$(CONFIG_ARMV8_PSCI) += smc_ecc_dbe_s10.o
+obj-$(CONFIG_ARMV8_PSCI) += smc_fpga_reconfig_s10.o
+obj-$(CONFIG_ARMV8_PSCI) += smc_registers_s10.o
+obj-$(CONFIG_ARMV8_PSCI) += smc_rsu_s10.o
+endif
endif
ifdef CONFIG_TARGET_SOCFPGA_AGILEX
@@ -49,11 +57,19 @@ obj-y += misc_soc64.o
obj-y += mmu-arm64_s10.o
obj-y += reset_manager_s10.o
obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH) += secure_vab.o
+obj-y += smmu_s10.o
obj-y += system_manager_soc64.o
obj-y += timer_s10.o
obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH) += vab.o
obj-y += wrap_handoff_soc64.o
obj-y += wrap_pll_config_soc64.o
+ifndef CONFIG_SPL_BUILD
+obj-$(CONFIG_ARMV8_PSCI) += psci.o
+obj-$(CONFIG_ARMV8_PSCI) += smc_ecc_dbe_s10.o
+obj-$(CONFIG_ARMV8_PSCI) += smc_fpga_reconfig_s10.o
+obj-$(CONFIG_ARMV8_PSCI) += smc_registers_s10.o
+obj-$(CONFIG_ARMV8_PSCI) += smc_rsu_s10.o
+endif
endif
ifdef CONFIG_TARGET_SOCFPGA_N5X
@@ -71,10 +87,6 @@ obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH) += vab.o
obj-y += wrap_handoff_soc64.o
obj-y += wrap_pll_config_soc64.o
ifndef CONFIG_SPL_BUILD
-obj-y += rsu.o
-obj-y += rsu_ll_qspi.o
-obj-y += rsu_misc.o
-obj-y += rsu_s10.o
obj-$(CONFIG_ARMV8_PSCI) += psci.o
obj-$(CONFIG_ARMV8_PSCI) += smc_ecc_dbe_s10.o
obj-$(CONFIG_ARMV8_PSCI) += smc_registers_s10.o
@@ -90,21 +102,20 @@ obj-y += wrap_iocsr_config.o
obj-y += wrap_pinmux_config.o
obj-y += wrap_sdram_config.o
endif
-ifdef CONFIG_TARGET_SOCFPGA_SOC64
-obj-y += firewall.o
-obj-y += spl_soc64.o
-endif
ifdef CONFIG_TARGET_SOCFPGA_ARRIA10
obj-y += spl_a10.o
endif
ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
obj-y += spl_s10.o
+obj-y += spl_soc64.o
endif
ifdef CONFIG_TARGET_SOCFPGA_AGILEX
obj-y += spl_agilex.o
+obj-y += spl_soc64.o
endif
ifdef CONFIG_TARGET_SOCFPGA_N5X
obj-y += spl_n5x.o
+obj-y += spl_soc64.o
endif
else
obj-$(CONFIG_SPL_ATF) += secure_reg_helper.o
@@ -117,4 +128,4 @@ CFLAGS_wrap_iocsr_config.o += -I$(srctree)/board/$(BOARDDIR)
CFLAGS_wrap_pinmux_config.o += -I$(srctree)/board/$(BOARDDIR)
CFLAGS_wrap_pll_config.o += -I$(srctree)/board/$(BOARDDIR)
CFLAGS_wrap_sdram_config.o += -I$(srctree)/board/$(BOARDDIR)
-endif
+endif
\ No newline at end of file
diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
index 4441649a31..c24319ffe5 100644
--- a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
+++ b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
@@ -16,6 +16,9 @@ void populate_sysmgr_pinmux(void);
#define SYSMGR_SOC64_DMA_PERIPH 0x24
#define SYSMGR_SOC64_SDMMC 0x28
#define SYSMGR_SOC64_SDMMC_L3MASTER 0x2c
+#define SYSMGR_SOC64_NANDGRP_L3MASTER 0x34
+#define SYSMGR_SOC64_USB0_L3MASTER 0x38
+#define SYSMGR_SOC64_USB1_L3MASTER 0x3c
#define SYSMGR_SOC64_EMAC_GLOBAL 0x40
#define SYSMGR_SOC64_EMAC0 0x44
#define SYSMGR_SOC64_EMAC1 0x48
diff --git a/arch/arm/mach-socfpga/spl_agilex.c b/arch/arm/mach-socfpga/spl_agilex.c
index c279f97cea..a2af30ee57 100644
--- a/arch/arm/mach-socfpga/spl_agilex.c
+++ b/arch/arm/mach-socfpga/spl_agilex.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2019 Intel Corporation <www.intel.com>
+ * Copyright (C) 2019-2022 Intel Corporation <www.intel.com>
*
*/
@@ -65,7 +65,12 @@ void board_init_f(ulong dummy)
print_reset_info();
cm_print_clock_quick_summary();
- firewall_setup();
+ ret = uclass_get_device_by_name(UCLASS_NOP, "socfpga-secreg", &dev);
+ if (ret) {
+ printf("Firewall & secure settings init failed: %d\n", ret);
+ hang();
+ }
+
ret = uclass_get_device(UCLASS_CACHE, 0, &dev);
if (ret) {
debug("CCU init failed: %d\n", ret);
diff --git a/arch/arm/mach-socfpga/spl_n5x.c b/arch/arm/mach-socfpga/spl_n5x.c
index 92037190e2..2abc722a3c 100644
--- a/arch/arm/mach-socfpga/spl_n5x.c
+++ b/arch/arm/mach-socfpga/spl_n5x.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2020-2021 Intel Corporation <www.intel.com>
+ * Copyright (C) 2020-2022 Intel Corporation <www.intel.com>
*
*/
@@ -73,7 +73,11 @@ void board_init_f(ulong dummy)
print_reset_info();
cm_print_clock_quick_summary();
- firewall_setup();
+ ret = uclass_get_device_by_name(UCLASS_NOP, "socfpga-secreg", &dev);
+ if (ret) {
+ printf("Firewall & secure settings init failed: %d\n", ret);
+ hang();
+ }
ret = uclass_get_device(UCLASS_CACHE, 0, &dev);
if (ret) {
diff --git a/arch/arm/mach-socfpga/spl_s10.c b/arch/arm/mach-socfpga/spl_s10.c
index 4044dc335e..da623df097 100644
--- a/arch/arm/mach-socfpga/spl_s10.c
+++ b/arch/arm/mach-socfpga/spl_s10.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
+ * Copyright (C) 2016-2022 Intel Corporation <www.intel.com>
*
*/
@@ -30,6 +30,7 @@ void board_init_f(ulong dummy)
{
const struct cm_config *cm_default_cfg = cm_get_default_config();
int ret;
+ struct udevice *dev;
ret = spl_early_init();
if (ret)
@@ -68,7 +69,11 @@ void board_init_f(ulong dummy)
print_reset_info();
cm_print_clock_quick_summary();
- firewall_setup();
+ ret = uclass_get_device_by_name(UCLASS_NOP, "socfpga-secreg", &dev);
+ if (ret) {
+ printf("Firewall & secure settings init failed: %d\n", ret);
+ hang();
+ }
/* disable ocram security at CCU for non secure access */
clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADMASK_MEM_RAM0),
@@ -77,8 +82,6 @@ void board_init_f(ulong dummy)
CCU_ADMASK_P_MASK | CCU_ADMASK_NS_MASK);
#if CONFIG_IS_ENABLED(ALTERA_SDRAM)
- struct udevice *dev;
-
ret = uclass_get_device(UCLASS_RAM, 0, &dev);
if (ret) {
debug("DRAM init failed: %d\n", ret);
diff --git a/configs/socfpga_agilex_nand_atf_defconfig b/configs/socfpga_agilex_nand_atf_defconfig
index fb92ff2514..58a28481f6 100755
--- a/configs/socfpga_agilex_nand_atf_defconfig
+++ b/configs/socfpga_agilex_nand_atf_defconfig
@@ -8,7 +8,6 @@ CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0x00200000
CONFIG_DM_GPIO=y
CONFIG_SPL_TEXT_BASE=0xffe00000
-CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_TARGET_SOCFPGA_AGILEX_SOCDK=y
CONFIG_IDENT_STRING="socfpga_agilex"
CONFIG_SPL_FS_FAT=y
diff --git a/configs/socfpga_agilex_nand_defconfig b/configs/socfpga_agilex_nand_defconfig
index 5613237ae5..f3b3c0b602 100755
--- a/configs/socfpga_agilex_nand_defconfig
+++ b/configs/socfpga_agilex_nand_defconfig
@@ -8,7 +8,6 @@ CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0x00200000
CONFIG_DM_GPIO=y
CONFIG_SPL_TEXT_BASE=0xffe00000
-CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_TARGET_SOCFPGA_AGILEX_SOCDK=y
CONFIG_IDENT_STRING="socfpga_agilex"
CONFIG_SPL_FS_FAT=y
diff --git a/configs/socfpga_n5x_atf_defconfig b/configs/socfpga_n5x_atf_defconfig
index d4e77f8147..5e94a923bc 100644
--- a/configs/socfpga_n5x_atf_defconfig
+++ b/configs/socfpga_n5x_atf_defconfig
@@ -97,6 +97,5 @@ CONFIG_WDT=y
CONFIG_PANIC_HANG=y
CONFIG_SHA512_ALGO=y
CONFIG_SHA384=y
-CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_FS_LOADER=y
CONFIG_SPL_ENV_SUPPORT=y
diff --git a/configs/socfpga_n5x_defconfig b/configs/socfpga_n5x_defconfig
index ede28f530e..1f69277c8c 100644
--- a/configs/socfpga_n5x_defconfig
+++ b/configs/socfpga_n5x_defconfig
@@ -85,7 +85,6 @@ CONFIG_WDT=y
CONFIG_PANIC_HANG=y
CONFIG_SHA512_ALGO=y
CONFIG_SHA384=y
-CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_FS_LOADER=y
CONFIG_SPL_ENV_SUPPORT=y
diff --git a/configs/socfpga_n5x_vab_defconfig b/configs/socfpga_n5x_vab_defconfig
index d2de1eccf5..0f55959a45 100644
--- a/configs/socfpga_n5x_vab_defconfig
+++ b/configs/socfpga_n5x_vab_defconfig
@@ -99,6 +99,5 @@ CONFIG_CMD_WDT=y
CONFIG_PANIC_HANG=y
CONFIG_SHA512_ALGO=y
CONFIG_SHA384=y
-CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_FS_LOADER=y
CONFIG_SPL_ENV_SUPPORT=y
diff --git a/configs/socfpga_stratix10_nand_atf_defconfig b/configs/socfpga_stratix10_nand_atf_defconfig
index a3fd9742e8..29c96bf6f1 100755
--- a/configs/socfpga_stratix10_nand_atf_defconfig
+++ b/configs/socfpga_stratix10_nand_atf_defconfig
@@ -9,7 +9,6 @@ CONFIG_ENV_OFFSET=0x00200000
CONFIG_SYS_SPI_U_BOOT_OFFS=0x02000000
CONFIG_DM_GPIO=y
CONFIG_SPL_TEXT_BASE=0xFFE00000
-CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_TARGET_SOCFPGA_STRATIX10_SOCDK=y
CONFIG_IDENT_STRING="socfpga_stratix10"
CONFIG_SPL_FS_FAT=y
diff --git a/configs/socfpga_agilex_nand_defconfig b/configs/socfpga_stratix10_nand_defconfig
old mode 100755
new mode 100644
similarity index 82%
copy from configs/socfpga_agilex_nand_defconfig
copy to configs/socfpga_stratix10_nand_defconfig
index 5613237ae5..f41d2dc82c
--- a/configs/socfpga_agilex_nand_defconfig
+++ b/configs/socfpga_stratix10_nand_defconfig
@@ -6,28 +6,27 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0x00200000
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x02000000
CONFIG_DM_GPIO=y
-CONFIG_SPL_TEXT_BASE=0xffe00000
-CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-CONFIG_TARGET_SOCFPGA_AGILEX_SOCDK=y
-CONFIG_IDENT_STRING="socfpga_agilex"
+CONFIG_SPL_TEXT_BASE=0xFFE00000
+CONFIG_TARGET_SOCFPGA_STRATIX10_SOCDK=y
+CONFIG_IDENT_STRING="socfpga_stratix10"
CONFIG_SPL_FS_FAT=y
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
# CONFIG_PSCI_RESET is not set
CONFIG_ARMV8_PSCI=y
-CONFIG_DEFAULT_DEVICE_TREE="socfpga_agilex_socdk_nand"
+CONFIG_DEFAULT_DEVICE_TREE="socfpga_stratix10_socdk_nand"
CONFIG_NAND_BOOT=y
CONFIG_BOOTDELAY=5
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="earlycon panic=-1"
CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="run nandload; run linux_qspi_enable; run nandboot"
+CONFIG_BOOTCOMMAND="run nandload; run linux_qspi_enable; run rsu_status; run nandboot"
CONFIG_SPL_MTD_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
-CONFIG_SPL_CACHE=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PROMPT="SOCFPGA_AGILEX # "
+CONFIG_SYS_PROMPT="SOCFPGA_STRATIX10 # "
CONFIG_CMD_MEMTEST=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
@@ -83,4 +82,5 @@ CONFIG_USB_DWC2=y
CONFIG_USB_STORAGE=y
CONFIG_DESIGNWARE_WATCHDOG=y
CONFIG_WDT=y
-# CONFIG_SPL_USE_TINY_PRINTF is not set
\ No newline at end of file
+# CONFIG_SPL_USE_TINY_PRINTF is not set
+CONFIG_PANIC_HANG=y
\ No newline at end of file
--
2.26.2
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