[PATCH 2/5] misc: socfpga_secreg: Enable register settings in DTS

[Jit Loon Lim]

From: Tien Fong Chee <tien.fong.chee at intel.com>

Enable register settings from device tree in SPL, which require high
privilege access like firewall registers. This also provides user a clean
interface and all register settings are centralized in one place, device
tree.

Signed-off-by: Tien Fong Chee <tien.fong.chee at intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim at intel.com>
---
 drivers/misc/Kconfig          |  9 ++++
 drivers/misc/Makefile         |  2 +
 drivers/misc/socfpga_secreg.c | 86 +++++++++++++++++++++++++++++++++++
 3 files changed, 97 insertions(+)
 create mode 100644 drivers/misc/socfpga_secreg.c

diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index a6da6e215d..d9da836675 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -645,4 +645,13 @@ config SL28CPLD
 	  the base driver which provides common access methods for the
 	  sub-drivers.
 
+config SPL_SOCFPGA_SEC_REG
+	bool "Enable register setting from device tree in SPL"
+	depends on SPL
+	help
+	  Enable register setting from device tree in SPL, which require
+	  high privilege access like firewall registers. This also
+	  provides user a clean interface and all register settings are
+	  centralized in one place, device tree.
+
 endmenu
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index d494639cd9..183d92b6e0 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -29,6 +29,7 @@ ifdef CONFIG_SPL_BUILD
 obj-$(CONFIG_SANDBOX) += spltest_sandbox.o
 endif
 endif
+
 obj-$(CONFIG_ALI152X) += ali512x.o
 obj-$(CONFIG_ALTERA_SYSID) += altera_sysid.o
 obj-$(CONFIG_ATSHA204A) += atsha204a-i2c.o
@@ -89,3 +90,4 @@ obj-$(CONFIG_K3_AVS0) += k3_avs.o
 obj-$(CONFIG_ESM_K3) += k3_esm.o
 obj-$(CONFIG_ESM_PMIC) += esm_pmic.o
 obj-$(CONFIG_SL28CPLD) += sl28cpld.o
+obj-$(CONFIG_SPL_SOCFPGA_SEC_REG) += socfpga_secreg.o
diff --git a/drivers/misc/socfpga_secreg.c b/drivers/misc/socfpga_secreg.c
new file mode 100644
index 0000000000..a4b297e7f1
--- /dev/null
+++ b/drivers/misc/socfpga_secreg.c
@@ -0,0 +1,86 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2021 Intel Corporation <www.intel.com>
+ *
+ */
+
+#include <asm/io.h>
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+
+static int socfpga_secreg_probe(struct udevice *dev)
+{
+	const fdt32_t *list;
+	fdt_addr_t offset, base;
+	fdt_val_t val, read_val;
+	int size, i;
+	u32 blk_sz, reg;
+	ofnode node;
+	const char *name = NULL;
+
+	debug("%s(dev=%p)\n", __func__, dev);
+
+	if (!dev_has_ofnode(dev))
+		return 0;
+
+	dev_for_each_subnode(node, dev) {
+		name = ofnode_get_name(node);
+		if (!name)
+			return -EINVAL;
+
+		if (ofnode_read_u32_index(node, "reg", 1, &blk_sz))
+			return -EINVAL;
+
+		base = ofnode_get_addr(node);
+		if (base == FDT_ADDR_T_NONE)
+			return -EINVAL;
+
+		debug("%s(node_offset 0x%lx node_name %s ", __func__,
+		      node.of_offset, name);
+		debug("node addr 0x%llx blk sz 0x%x)\n", base, blk_sz);
+
+		list = ofnode_read_prop(node, "intel,offset-settings", &size);
+		if (!list)
+			return -EINVAL;
+
+		debug("%s(intel,offset-settings property size=%x)\n", __func__,
+		      size);
+		size /= sizeof(*list) * 2;
+		for (i = 0; i < size; i++) {
+			offset = fdt32_to_cpu(*list++);
+			val = fdt32_to_cpu(*list++);
+			debug("%s(intel,offset-settings 0x%llx : 0x%llx)\n",
+			      __func__, offset, val);
+
+			if (blk_sz <= offset) {
+				printf("%s: Overflow as offset 0x%llx",
+				       __func__, offset);
+				printf(" is larger than block size 0x%x\n",
+				       blk_sz);
+				return -EINVAL;
+			}
+
+			reg = base + offset;
+			writel(val, (uintptr_t)reg);
+
+			read_val = readl((uintptr_t)reg);
+			debug("%s(reg 0x%x = wr : 0x%llx  rd : 0x%llx)\n",
+			      __func__, reg, val, read_val);
+		}
+	}
+
+	return 0;
+};
+
+static const struct udevice_id socfpga_secreg_ids[] = {
+	{.compatible = "intel,socfpga-secreg"},
+	{ }
+};
+
+U_BOOT_DRIVER(socfpga_secreg) = {
+	.name		= "socfpga-secreg",
+	.id		= UCLASS_NOP,
+	.of_match	= socfpga_secreg_ids,
+	.probe		= socfpga_secreg_probe,
+};
-- 
2.26.2