[PATCH v2 09/25] phy: cadence: Sierra: Model PLL_CMNLC and PLL_CMNLC1 as a clock

Tom Rini trini at konsulko.com
Tue Feb 8 18:34:37 CET 2022

On Fri, Jan 28, 2022 at 01:41:36PM +0530, Aswath Govindraju wrote:

> Sierra has two PLLs, PLL_CMNLC and PLL_CMNLC1 and each of these PLLs has
> two inputs, plllc_refclk (input from pll0_refclk) and refrcv (input from
> pll1_refclk). Model PLL_CMNLC and PLL_CMNLC1 as a clock so that it's
> possible to select one of these two inputs from device tree.
> Signed-off-by: Aswath Govindraju <a-govindraju at ti.com>

Applied to u-boot/master, thanks!

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