[PATCH v2 20/25] phy: cadence: Sierra: Update single link PCIe register configuration

[Tom Rini]

On Fri, Jan 28, 2022 at 01:41:47PM +0530, Aswath Govindraju wrote:

> From: Swapnil Jakhade <sjakhade at cadence.com>
> 
> Add single link PCIe register configurations for no SSC and internal
> SSC. Also, add missing PMA lane registers for external SSC.
> 
> Signed-off-by: Swapnil Jakhade <sjakhade at cadence.com>
> Signed-off-by: Aswath Govindraju <a-govindraju at ti.com>

Applied to u-boot/master, thanks!

-- 
Tom
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