[PATCH 6/7] microblaze: exception: fix unaligned data access register mask

[Ovidiu Panait]

The correct mask for getting the source/destination register from ESR in
the case of an unaligned access exception is 0x3E0. With this change, a
dummy unaligned store produces the expected info:
"""
>> swi r5, r0, 0x111

 ...
 Hardware exception at 0x111 address
 Unaligned data access exception
 Unaligned word access
 Unaligned store access
 Register R5
 Return address from exception 0x7f99dfc
 ### ERROR ### Please RESET the board ###
"""

Signed-off-by: Ovidiu Panait <ovidiu.panait at windriver.com>
---

 arch/microblaze/cpu/exception.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/microblaze/cpu/exception.c b/arch/microblaze/cpu/exception.c
index d37f04364a..d3640d3903 100644
--- a/arch/microblaze/cpu/exception.c
+++ b/arch/microblaze/cpu/exception.c
@@ -38,7 +38,7 @@ void _hw_exception_handler (void)
 
 		printf("Unaligned %sword access\n", ((state & 0x800) ? "" : "half"));
 		printf("Unaligned %s access\n", ((state & 0x400) ? "store" : "load"));
-		printf("Register R%x\n", (state & 0x3E) >> 5);
+		printf("Register R%x\n", (state & 0x3E0) >> 5);
 		break;
 	case 0x2:
 		puts("Illegal op-code exception\n");
-- 
2.25.1