[PATCH] riscv: fix build with binutils 2.38

Khem Raj raj.khem at gmail.com
Mon Feb 14 06:31:09 CET 2022

>From version 2.38, binutils default to ISA spec version 20191213. This
means that the csr read/write (csrr*/csrw*) instructions and fence.i
instruction has separated from the `I` extension, become two standalone
extensions: Zicsr and Zifencei.

The fix is to specify those extensions explicitly in -march. However as
older binutils version do not support this, we first need to detect

arch/riscv/lib/cache.c: Assembler messages:
arch/riscv/lib/cache.c:12: Error: unrecognized opcode `fence.i'

Signed-off-by: Khem Raj <raj.khem at gmail.com>
Cc: Rick Chen <rick at andestech.com>
Cc: Leo <ycliang at andestech.com>
 arch/riscv/Makefile | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile
index 0b80eb8d86..e6fe1fc02b 100644
--- a/arch/riscv/Makefile
+++ b/arch/riscv/Makefile
@@ -24,7 +24,12 @@ ifeq ($(CONFIG_CMODEL_MEDANY),y)
 	CMODEL = medany
-ARCH_FLAGS = -march=$(ARCH_BASE)$(ARCH_A)$(ARCH_C) -mabi=$(ABI) \
+# Newer binutils versions default to ISA spec version 20191213 which moves some
+# instructions from the I extension to the Zicsr and Zifencei extensions.
+toolchain-need-zicsr-zifencei := $(call cc-option-yn, -march=$(ARCH_BASE)$(ARCH_A)$(ARCH_C)_zicsr_zifencei)
+zicsr_zifencei-$(toolchain-need-zicsr-zifencei) := _zicsr_zifencei
+ARCH_FLAGS = -march=$(ARCH_BASE)$(ARCH_A)$(ARCH_C)$(zicsr_zifencei-y) -mabi=$(ABI) \

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