[PATCH] riscv: fix build with binutils 2.38

[Leo Liang]

Hi Khem,
On Sun, Feb 13, 2022 at 09:28:45PM -0800, Khem Raj wrote:
> From version 2.38, binutils default to ISA spec version 20191213. This
> means that the csr read/write (csrr*/csrw*) instructions and fence.i
> instruction has separated from the `I` extension, become two standalone
> extensions: Zicsr and Zifencei.
> 
> The fix is to specify those extensions explicitly in -march. However as
> older binutils version do not support this, we first need to detect
> that.
> 
> Fixes
> arch/riscv/lib/cache.c: Assembler messages:
> arch/riscv/lib/cache.c:12: Error: unrecognized opcode `fence.i'
> 
> Signed-off-by: Khem Raj <raj.khem at gmail.com>
> Cc: Rick Chen <rick at andestech.com>
> Cc: Leo <ycliang at andestech.com>

Thanks for sending the patch.

As Alexandre has already sent out a patch to solve this problem first,
(https://patchwork.ozlabs.org/project/uboot/patch/20220128134713.2322800-1-alexandre.ghiti@canonical.com/)
we'd go with this patch and we welcome your future patches to improve RISC-V U-Boot.

Best regards,
Leo