[PATCH] riscv: Fix build against binutils 2.38

[Alexandre Ghiti]

Hi Leo,

On Thu, Feb 17, 2022 at 10:25 AM Leo Liang <ycliang at andestech.com> wrote:
>
> Hi Alexandre,
> On Fri, Jan 28, 2022 at 02:47:13PM +0100, Alexandre Ghiti wrote:
> > The following description is copied from the equivalent patch for the
> > Linux Kernel proposed by Aurelien Jarno:
> >
> > From version 2.38, binutils default to ISA spec version 20191213. This
> > means that the csr read/write (csrr*/csrw*) instructions and fence.i
> > instruction has separated from the `I` extension, become two standalone
> > extensions: Zicsr and Zifencei. As the kernel uses those instruction,
> > this causes the following build failure:
> >
> > arch/riscv/cpu/mtrap.S: Assembler messages:
> > arch/riscv/cpu/mtrap.S:65: Error: unrecognized opcode `csrr a0,scause'
> > arch/riscv/cpu/mtrap.S:66: Error: unrecognized opcode `csrr a1,sepc'
> > arch/riscv/cpu/mtrap.S:67: Error: unrecognized opcode `csrr a2,stval'
> > arch/riscv/cpu/mtrap.S:70: Error: unrecognized opcode `csrw sepc,a0'
> >
> > Signed-off-by: Alexandre Ghiti <alexandre.ghiti at canonical.com>
> > ---
> >  arch/riscv/Makefile | 11 ++++++++++-
> >  1 file changed, 10 insertions(+), 1 deletion(-)
>
> This patch seems to fail CI somehow.
> (https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/11004)
>
> Could you take a look at it ?

I have just tried on master (commit ab8903a24db1) and it failed for
the same reason, so this is not related to this patch. Nevertheless,
I'll try to bisect the problem :)

Thanks,

Alex

>
> Best regards,
> Leo