[PATCH v2 1/2] ram: stm32mp1: Unconditionally enable ASR

[Patrice CHOTARD]

Hi Marek

one minor remark

On 2/21/22 21:55, Marek Vasut wrote:
> Enable DRAM ASR, auto self-refresh, unconditionally. This saves non-trivial
> amount of power both at runtime and in suspend (on 2x W632GU6NB-15 ~150mW).
> 
> Signed-off-by: Marek Vasut <marex at denx.de>
> Cc: Patrick Delaunay <patrick.delaunay at foss.st.com>
> Cc: Patrice Chotard <patrice.chotard at foss.st.com>
> ---
> V2: Rebase on latest changes in this driver past v2022.01
> ---
>  drivers/ram/stm32mp1/stm32mp1_ddr.c      | 25 ++++++++++++++++++++++++
>  drivers/ram/stm32mp1/stm32mp1_ddr_regs.h |  6 ++++++
>  2 files changed, 31 insertions(+)
> 
> diff --git a/drivers/ram/stm32mp1/stm32mp1_ddr.c b/drivers/ram/stm32mp1/stm32mp1_ddr.c
> index 4d78aa5cb13..04fc8eab909 100644
> --- a/drivers/ram/stm32mp1/stm32mp1_ddr.c
> +++ b/drivers/ram/stm32mp1/stm32mp1_ddr.c
> @@ -27,6 +27,8 @@
>  #define RCC_DDRITFCR_DPHYAPBRST		(BIT(17))
>  #define RCC_DDRITFCR_DPHYRST		(BIT(18))
>  #define RCC_DDRITFCR_DPHYCTLRST		(BIT(19))
> +#define RCC_DDRITFCR_DDRCKMOD_MASK	(0x7 << 20)
> +#define RCC_DDRITFCR_DDRCKMOD_ASR	(0x1 << 20)

#define RCC_DDRITFCR_DDRCKMOD_MASK	GENMASK(22, 20)
#define RCC_DDRITFCR_DDRCKMOD_ASR	BIT(20)

>  
>  struct reg_desc {
>  	const char *name;
> @@ -651,6 +653,26 @@ static void stm32mp1_refresh_restore(struct stm32mp1_ddrctl *ctl,
>  	wait_sw_done_ack(ctl);
>  }
>  
> +static void stm32mp1_asr_enable(struct ddr_info *priv)
> +{
> +	struct stm32mp1_ddrctl *ctl = priv->ctl;
> +
> +	clrsetbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCKMOD_MASK,
> +			RCC_DDRITFCR_DDRCKMOD_ASR);
> +
> +	start_sw_done(ctl);
> +
> +	setbits_le32(&ctl->hwlpctl, DDRCTRL_HWLPCTL_HW_LP_EN);
> +	writel(DDRCTRL_PWRTMG_POWERDOWN_TO_X32(0x10) |
> +	       DDRCTRL_PWRTMG_SELFREF_TO_X32(0x01),
> +	       &ctl->pwrtmg);
> +	setbits_le32(&ctl->pwrctl, DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE);
> +	setbits_le32(&ctl->pwrctl, DDRCTRL_PWRCTL_SELFREF_EN);
> +
> +	setbits_le32(&ctl->dfimisc, DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN);
> +	wait_sw_done_ack(ctl);
> +}
> +
>  /* board-specific DDR power initializations. */
>  __weak int board_ddr_power_init(enum ddr_type ddr_type)
>  {
> @@ -822,6 +844,9 @@ start:
>  	stm32mp1_refresh_restore(priv->ctl, config->c_reg.rfshctl3,
>  				 config->c_reg.pwrctl);
>  
> +/* Enable auto-self-refresh, which saves a bit of power at runtime. */
> +	stm32mp1_asr_enable(priv);
> +
>  	/* enable uMCTL2 AXI port 0 and 1 */
>  	setbits_le32(&priv->ctl->pctrl_0, DDRCTRL_PCTRL_N_PORT_EN);
>  	setbits_le32(&priv->ctl->pctrl_1, DDRCTRL_PCTRL_N_PORT_EN);
> diff --git a/drivers/ram/stm32mp1/stm32mp1_ddr_regs.h b/drivers/ram/stm32mp1/stm32mp1_ddr_regs.h
> index f1a26e31f6c..42be1ba57c7 100644
> --- a/drivers/ram/stm32mp1/stm32mp1_ddr_regs.h
> +++ b/drivers/ram/stm32mp1/stm32mp1_ddr_regs.h
> @@ -265,8 +265,14 @@ struct stm32mp1_ddrphy {
>  
>  #define DDRCTRL_PWRCTL_SELFREF_EN		BIT(0)
>  #define DDRCTRL_PWRCTL_POWERDOWN_EN		BIT(1)
> +#define DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE	BIT(3)
>  #define DDRCTRL_PWRCTL_SELFREF_SW		BIT(5)
>  
> +#define DDRCTRL_PWRTMG_SELFREF_TO_X32(n)	(((n) & 0xff) << 16)
> +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32(n)	((n) & 0x1f)
> +
> +#define DDRCTRL_HWLPCTL_HW_LP_EN		BIT(0)
> +
>  #define DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH	BIT(0)
>  
>  #define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_MASK	GENMASK(27, 16)
Reviewed-by: Patrice Chotard <patrice.chotard at foss.st.com>

Thanks
Patrice