[PATCH] net: fsl_mdio: Fix busy flag polling register
Ioana Ciornei
ioana.ciornei at nxp.com
Tue Jan 4 15:24:14 CET 2022
On Sun, Jan 02, 2022 at 06:34:18PM +0100, Markus Koch wrote:
> NXP's mEMAC reference manual, Chapter 6.5.5 "MDIO Ethernet Management
> Interface usage", specifies to poll the BSY (0) bit in the CFG (we call
> it CTL) register to wait until a transaction has finished, not bit 31 in
> the data register.
First of all, the CFG (Configuration) and CTL (Control) are two
different registers so the '(we call it CTL)' part of your statement is
false.
Indeed, the BSY bit is located in the MDIO_CFG register but that is not
accessed through the mdio_ctl field as you used it in your changes.
It's instead accessed through the mdio_stat field (the MDIO_CFG is
called in some RMs as the Configuration and Status register).
>
> In the Linux kernel, this has already been fixed in commit 26eee0210ad7
> ("net/fsl: fix a bug in xgmac_mdio").
>
Even the commit that you referenced is using the mdio_stat field.
--- a/drivers/net/ethernet/freescale/xgmac_mdio.c
+++ b/drivers/net/ethernet/freescale/xgmac_mdio.c
@@ -79,7 +79,7 @@ static int xgmac_wait_until_done(struct device *dev,
/* Wait till the MDIO write is complete */
timeout = TIMEOUT;
- while ((ioread32be(®s->mdio_data) & MDIO_DATA_BSY) && timeout) {
+ while ((ioread32be(®s->mdio_stat) & MDIO_STAT_BSY) && timeout) {
cpu_relax();
timeout--;
}
Please fix this up in a v2.
Thanks,
Ioana
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