[PATCH v2 7/8] arm: kirkwood: Pogoplug-V4 : Add board implementation
Stefan Roese
sr at denx.de
Thu Jan 13 14:38:38 CET 2022
On 12/23/21 08:26, Tony Dinh wrote:
> Add board implementation for Pogoplug V4
>
> Note: currently the fdt_get_phy_addr function in this file is
> duplicate in this board and many other Kirkwood boards
> (eg. Sheevaplug, GoFlex Home, etc.). This function is being
> factored out into common area by another patch. And because it
> was written for flattree only, the patch is being rewritten to
> use livetree calls.
>
> Signed-off-by: Tony Dinh <mibodhi at gmail.com>
> ---
>
> Changes in v2:
> Merge constants from header file.
>
> board/cloudengines/pogo_v4/pogo_v4.c | 220 +++++++++++++++++++++++++++
> 1 file changed, 220 insertions(+)
> create mode 100644 board/cloudengines/pogo_v4/pogo_v4.c
Ups. And now you bring in the C file for the Makefile from patch 6/8?
This will make problems with git bi-secting. Please squash both patches
into one instead.
Thanks,
Stefan
> diff --git a/board/cloudengines/pogo_v4/pogo_v4.c b/board/cloudengines/pogo_v4/pogo_v4.c
> new file mode 100644
> index 0000000000..c85de0b22e
> --- /dev/null
> +++ b/board/cloudengines/pogo_v4/pogo_v4.c
> @@ -0,0 +1,220 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2014-2021 Tony Dinh <mibodhi at gmail.com>
> + *
> + * Based on
> + * Copyright (C) 2012 David Purdy <david.c.purdy at gmail.com>
> + *
> + * Based on Kirkwood support:
> + * (C) Copyright 2009
> + * Marvell Semiconductor <www.marvell.com>
> + * Written-by: Prafulla Wadaskar <prafulla at marvell.com>
> + */
> +
> +#include <common.h>
> +#include <miiphy.h>
> +#include <asm/arch/cpu.h>
> +#include <asm/arch/soc.h>
> +#include <asm/arch/mpp.h>
> +#include <asm/io.h>
> +#include <asm/arch/gpio.h>
> +#include <asm/mach-types.h>
> +#include <bootstage.h>
> +#include <command.h>
> +#include <init.h>
> +#include <linux/bitops.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +/* GPIO configuration */
> +#define POGO_V4_OE_LOW (~(0))
> +#define POGO_V4_OE_HIGH (~(0))
> +#define POGO_V4_OE_VAL_LOW BIT(29)
> +#define POGO_V4_OE_VAL_HIGH 0
> +
> +/* PHY related */
> +#define MV88E1116_LED_FCTRL_REG 10
> +#define MV88E1116_CPRSP_CR3_REG 21
> +#define MV88E1116_MAC_CTRL_REG 21
> +#define MV88E1116_PGADR_REG 22
> +#define MV88E1116_RGMII_TXTM_CTRL BIT(4)
> +#define MV88E1116_RGMII_RXTM_CTRL BIT(5)
> +
> +/* button */
> +#define BTN_EJECT 29
> +
> +int board_early_init_f(void)
> +{
> + /*
> + * default gpio configuration
> + * There are maximum 64 gpios controlled through 2 sets of registers
> + * the below configuration configures mainly initial LED status
> + */
> + mvebu_config_gpio(POGO_V4_OE_VAL_LOW,
> + POGO_V4_OE_VAL_HIGH,
> + POGO_V4_OE_LOW, POGO_V4_OE_HIGH);
> +
> + /* Multi-Purpose Pins Functionality configuration */
> + u32 kwmpp_config[] = {
> + MPP0_NF_IO2,
> + MPP1_NF_IO3,
> + MPP2_NF_IO4,
> + MPP3_NF_IO5,
> + MPP4_NF_IO6,
> + MPP5_NF_IO7,
> + MPP6_SYSRST_OUTn,
> + MPP7_GPO,
> + MPP8_TW_SDA,
> + MPP9_TW_SCK,
> + MPP10_UART0_TXD,
> + MPP11_UART0_RXD,
> + MPP12_SD_CLK,
> + MPP13_SD_CMD,
> + MPP14_SD_D0,
> + MPP15_SD_D1,
> + MPP16_SD_D2,
> + MPP17_SD_D3,
> + MPP18_NF_IO0,
> + MPP19_NF_IO1,
> + MPP20_SATA1_ACTn,
> + MPP21_SATA0_ACTn,
> + MPP22_GPIO, /* Green LED */
> + MPP23_GPIO,
> + MPP24_GPIO, /* Red LED */
> + MPP25_GPIO,
> + MPP26_GPIO,
> + MPP27_GPIO,
> + MPP28_GPIO,
> + MPP29_GPIO, /* Eject button */
> + MPP30_GPIO,
> + MPP31_GPIO,
> + MPP32_GPIO,
> + MPP33_GPIO,
> + MPP34_GPIO,
> + MPP35_GPIO, /* FR6192 has only 36 GPIOs */
> + 0
> + };
> + kirkwood_mpp_conf(kwmpp_config, NULL);
> +
> + return 0;
> +}
> +
> +int board_late_init(void)
> +{
> + /* Do late init to ensure successful enumeration of XHCI devices */
> + pci_init();
> + return 0;
> +}
> +
> +int board_init(void)
> +{
> + /* Boot parameters address */
> + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
> +
> + return 0;
> +}
> +
> +int fdt_get_phy_addr(const char *path)
> +{
> + const void *fdt = gd->fdt_blob;
> + const u32 *reg;
> + const u32 *val;
> + int node, phandle, addr;
> +
> + /* Find the node by its full path */
> + node = fdt_path_offset(fdt, path);
> + if (node >= 0) {
> + /* Look up phy-handle */
> + val = fdt_getprop(fdt, node, "phy-handle", NULL);
> + if (!val) {
> + /* Look up phy (deprecated property for phy handle) */
> + val = fdt_getprop(fdt, node, "phy", NULL);
> + }
> + if (val) {
> + phandle = fdt32_to_cpu(*val);
> + if (!phandle)
> + return -FDT_ERR_NOTFOUND;
> +
> + /* Follow it to its node */
> + node = fdt_node_offset_by_phandle(fdt, phandle);
> + if (node) {
> + /* Look up reg */
> + reg = fdt_getprop(fdt, node, "reg", NULL);
> + if (reg) {
> + addr = fdt32_to_cpu(*reg);
> + return addr;
> + }
> + }
> + }
> + }
> + return -FDT_ERR_NOTFOUND;
> +}
> +
> +#if defined(CONFIG_RESET_PHY_R)
> +/* Configure and initialize PHY */
> +void reset_phy(void)
> +{
> + u16 reg;
> + int phyaddr;
> + char *name = "ethernet-controller at 72000";
> + char *eth0_path = "/ocp at f1000000/ethernet-controller at 72000";
> +
> + if (miiphy_set_current_dev(name))
> + return;
> +
> + phyaddr = fdt_get_phy_addr(eth0_path);
> + if (phyaddr < 0)
> + return;
> +
> + /*
> + * Enable RGMII delay on Tx and Rx for CPU port
> + * Ref: sec 4.7.2 of chip datasheet
> + */
> + miiphy_write(name, phyaddr, MV88E1116_PGADR_REG, 2);
> + miiphy_read(name, phyaddr, MV88E1116_MAC_CTRL_REG, ®);
> + reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
> + miiphy_write(name, phyaddr, MV88E1116_MAC_CTRL_REG, reg);
> + miiphy_write(name, phyaddr, MV88E1116_PGADR_REG, 0);
> +
> + /* reset the phy */
> + miiphy_reset(name, phyaddr);
> +
> + printf("88E1116 Initialized on %s\n", name);
> +}
> +#endif /* CONFIG_RESET_PHY_R */
> +
> +#if CONFIG_IS_ENABLED(BOOTSTAGE)
> +#define GREEN_LED BIT(22)
> +#define RED_LED BIT(24)
> +#define BOTH_LEDS (GREEN_LED | RED_LED)
> +#define NEITHER_LED 0
> +
> +static void set_leds(u32 leds, u32 blinking)
> +{
> + struct kwgpio_registers *r;
> + u32 oe;
> + u32 bl;
> +
> + r = (struct kwgpio_registers *)MVEBU_GPIO0_BASE;
> + oe = readl(&r->oe) | BOTH_LEDS;
> + writel(oe & ~leds, &r->oe); /* active low */
> + bl = readl(&r->blink_en) & ~BOTH_LEDS;
> + writel(bl | blinking, &r->blink_en);
> +}
> +
> +void show_boot_progress(int val)
> +{
> + switch (val) {
> + case BOOTSTAGE_ID_RUN_OS: /* booting Linux */
> + set_leds(BOTH_LEDS, NEITHER_LED);
> + break;
> + case BOOTSTAGE_ID_NET_ETH_START: /* Ethernet initialization */
> + set_leds(GREEN_LED, GREEN_LED);
> + break;
> + default:
> + if (val < 0) /* error */
> + set_leds(RED_LED, RED_LED);
> + break;
> + }
> +}
> +#endif
>
Viele Grüße,
Stefan Roese
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: sr at denx.de
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