FIT image: load secure FPGA

[Jorge Ramirez-Ortiz, Foundries]

On 19/01/22, Jorge Ramirez-Ortiz, Foundries wrote:
> On 19/01/22, Adrian Fiergolski wrote:
> > Hi Jorge,
> 
> hi Adrian,
> 
> > 
> > Have you succeeded to enable secure boot on ZynqMP with SPL (not Xilinx's
> > FSBL)? Is it documented somewhere? Any configuration files/yocto recipes?
> 
> somewhere there:
> https://github.com/foundriesio/meta-lmp
> 
> > Have you managed to resolve problem of the bitstream loaded in such a case
> > by SPL?
> >
> 
> Yes. I wrote the docs here below:
> https://docs.foundries.io/latest/reference-manual/security/authentication-xilinx.html
>

this might help you as well if you use OP-TEE and require RPMB access.

https://github.com/OP-TEE/optee_os/pull/4874



> 
> > I need to use an encrypted bitstream. However, it required the use of
> > DeviceKeys in post-boot state which eventually requires secure boot.
> > 
> > Regards,
> 
> hope that helps
> 
> > 
> > Adrian
> >