[PATCH v3 05/20] arm: K3: Add basic support for J721S2 SoC definition
Suman Anna
s-anna at ti.com
Wed Jan 19 19:15:34 CET 2022
Hi Aswath,
On 1/18/22 1:27 AM, Aswath Govindraju wrote:
> From: David Huang <d-huang at ti.com>
>
> Add basic support for J721S2 SoC definition
>
> Signed-off-by: David Huang <d-huang at ti.com>
> Signed-off-by: Aswath Govindraju <a-govindraju at ti.com>
> Signed-off-by: Dave Gerlach <d-gerlach at ti.com>
> Signed-off-by: Nishanth Menon <nm at ti.com>
> Signed-off-by: Hari Nagalla <hnagalla at ti.com>
> ---
> arch/arm/mach-k3/Kconfig | 15 +-
> arch/arm/mach-k3/Makefile | 1 +
> arch/arm/mach-k3/arm64-mmu.c | 53 +++
> arch/arm/mach-k3/include/mach/hardware.h | 4 +
> .../mach-k3/include/mach/j721s2_hardware.h | 60 +++
> arch/arm/mach-k3/include/mach/j721s2_spl.h | 46 ++
> arch/arm/mach-k3/include/mach/spl.h | 4 +
> arch/arm/mach-k3/j721s2/Makefile | 5 +
> arch/arm/mach-k3/j721s2/clk-data.c | 403 ++++++++++++++++++
> arch/arm/mach-k3/j721s2/dev-data.c | 85 ++++
> arch/arm/mach-k3/j721s2_init.c | 312 ++++++++++++++
> include/configs/j721s2_evm.h | 191 +++++++++
> 12 files changed, 1174 insertions(+), 5 deletions(-)
> create mode 100644 arch/arm/mach-k3/include/mach/j721s2_hardware.h
> create mode 100644 arch/arm/mach-k3/include/mach/j721s2_spl.h
> create mode 100644 arch/arm/mach-k3/j721s2/Makefile
> create mode 100644 arch/arm/mach-k3/j721s2/clk-data.c
> create mode 100644 arch/arm/mach-k3/j721s2/dev-data.c
> create mode 100644 arch/arm/mach-k3/j721s2_init.c
> create mode 100644 include/configs/j721s2_evm.h
>
> diff --git a/arch/arm/mach-k3/Kconfig b/arch/arm/mach-k3/Kconfig
> index 526f5f8b76c2..a01bf2351499 100644
> --- a/arch/arm/mach-k3/Kconfig
> +++ b/arch/arm/mach-k3/Kconfig
> @@ -10,6 +10,9 @@ config SOC_K3_AM6
> config SOC_K3_J721E
> bool "TI's K3 based J721E SoC Family Support"
>
> +config SOC_K3_J721S2
> + bool "TI's K3 based J721S2 SoC Family Support"
> +
> config SOC_K3_AM642
> bool "TI's K3 based AM642 SoC Family Support"
>
> @@ -21,7 +24,7 @@ config SYS_SOC
> config SYS_K3_NON_SECURE_MSRAM_SIZE
> hex
> default 0x80000 if SOC_K3_AM6
> - default 0x100000 if SOC_K3_J721E
> + default 0x100000 if SOC_K3_J721E || SOC_K3_J721S2
> default 0x1c0000 if SOC_K3_AM642
> help
> Describes the total size of the MCU or OCMC MSRAM present on
> @@ -32,7 +35,7 @@ config SYS_K3_NON_SECURE_MSRAM_SIZE
> config SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE
> hex
> default 0x58000 if SOC_K3_AM6
> - default 0xc0000 if SOC_K3_J721E
> + default 0xc0000 if SOC_K3_J721E || SOC_K3_J721S2
> default 0x180000 if SOC_K3_AM642
> help
> Describes the maximum size of the image that ROM can download
> @@ -41,14 +44,14 @@ config SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE
> config SYS_K3_MCU_SCRATCHPAD_BASE
> hex
> default 0x40280000 if SOC_K3_AM6
> - default 0x40280000 if SOC_K3_J721E
> + default 0x40280000 if SOC_K3_J721E || SOC_K3_J721S2
> help
> Describes the base address of MCU Scratchpad RAM.
>
> config SYS_K3_MCU_SCRATCHPAD_SIZE
> hex
> default 0x200 if SOC_K3_AM6
> - default 0x200 if SOC_K3_J721E
> + default 0x200 if SOC_K3_J721E || SOC_K3_J721S2
> help
> Describes the size of MCU Scratchpad RAM.
>
> @@ -56,6 +59,7 @@ config SYS_K3_BOOT_PARAM_TABLE_INDEX
> hex
> default 0x41c7fbfc if SOC_K3_AM6
> default 0x41cffbfc if SOC_K3_J721E
> + default 0x41cfdbfc if SOC_K3_J721S2
> default 0x701bebfc if SOC_K3_AM642
> help
> Address at which ROM stores the value which determines if SPL
> @@ -156,7 +160,7 @@ config K3_ATF_LOAD_ADDR
>
> config K3_DM_FW
> bool "Separate DM firmware image"
> - depends on SPL && CPU_V7R && SOC_K3_J721E && !CLK_TI_SCI && !TI_SCI_POWER_DOMAIN
> + depends on SPL && CPU_V7R && (SOC_K3_J721E || SOC_K3_J721S2) && !CLK_TI_SCI && !TI_SCI_POWER_DOMAIN
> default y
> help
> Enabling this will indicate that the system has separate DM
> @@ -169,4 +173,5 @@ source "board/ti/am65x/Kconfig"
> source "board/ti/am64x/Kconfig"
> source "board/ti/j721e/Kconfig"
> source "board/siemens/iot2050/Kconfig"
> +source "board/ti/j721s2/Kconfig"
> endif
> diff --git a/arch/arm/mach-k3/Makefile b/arch/arm/mach-k3/Makefile
> index 47cf7b6d17a8..c0a6a9c87d8f 100644
> --- a/arch/arm/mach-k3/Makefile
> +++ b/arch/arm/mach-k3/Makefile
> @@ -5,6 +5,7 @@
>
> obj-$(CONFIG_SOC_K3_AM6) += am6_init.o
> obj-$(CONFIG_SOC_K3_J721E) += j721e_init.o j721e/ j7200/
> +obj-$(CONFIG_SOC_K3_J721S2) += j721s2_init.o j721s2/
> obj-$(CONFIG_SOC_K3_AM642) += am642_init.o
> obj-$(CONFIG_ARM64) += arm64-mmu.o
> obj-$(CONFIG_CPU_V7R) += r5_mpu.o lowlevel_init.o
> diff --git a/arch/arm/mach-k3/arm64-mmu.c b/arch/arm/mach-k3/arm64-mmu.c
> index 94242e1e5cc3..c7f455c8818a 100644
> --- a/arch/arm/mach-k3/arm64-mmu.c
> +++ b/arch/arm/mach-k3/arm64-mmu.c
> @@ -181,6 +181,59 @@ struct mm_region *mem_map = j7200_mem_map;
>
> #endif /* CONFIG_SOC_K3_J721E */
>
> +#ifdef CONFIG_SOC_K3_J721S2
> +#define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 5)
> +
> +/* ToDo: Add 64bit IO */
> +struct mm_region j721s2_mem_map[NR_MMU_REGIONS] = {
> + {
> + .virt = 0x0UL,
> + .phys = 0x0UL,
> + .size = 0x80000000UL,
> + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
> + PTE_BLOCK_NON_SHARE |
> + PTE_BLOCK_PXN | PTE_BLOCK_UXN
> + }, {
> + .virt = 0x80000000UL,
> + .phys = 0x80000000UL,
> + .size = 0x20000000UL,
> + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
> + PTE_BLOCK_INNER_SHARE
> + }, {
> + .virt = 0xa0000000UL,
> + .phys = 0xa0000000UL,
> + .size = 0x04800000UL,
> + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
> + PTE_BLOCK_NON_SHARE
These addresses do not cater to the remoteprocs on J721S2. They look to be
copied from J7200, which has lot less cores. There are issues loading and
booting firmwares consistently on couple of different cores.
regards
Suman
> + }, {
> + .virt = 0xa4800000UL,
> + .phys = 0xa4800000UL,
> + .size = 0x5b800000UL,
> + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
> + PTE_BLOCK_INNER_SHARE
> + }, {
> + .virt = 0x880000000UL,
> + .phys = 0x880000000UL,
> + .size = 0x80000000UL,
> + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
> + PTE_BLOCK_INNER_SHARE
> + }, {
> + .virt = 0x500000000UL,
> + .phys = 0x500000000UL,
> + .size = 0x400000000UL,
> + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
> + PTE_BLOCK_NON_SHARE |
> + PTE_BLOCK_PXN | PTE_BLOCK_UXN
> + }, {
> + /* List terminator */
> + 0,
> + }
> +};
> +
> +struct mm_region *mem_map = j721s2_mem_map;
> +
> +#endif /* CONFIG_SOC_K3_J721S2 */
> +
> #ifdef CONFIG_SOC_K3_AM642
> /* NR_DRAM_BANKS + 32bit IO + 64bit IO + terminator */
> #define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 3)
> diff --git a/arch/arm/mach-k3/include/mach/hardware.h b/arch/arm/mach-k3/include/mach/hardware.h
> index 8725e7d51a5b..5c1265ffe949 100644
> --- a/arch/arm/mach-k3/include/mach/hardware.h
> +++ b/arch/arm/mach-k3/include/mach/hardware.h
> @@ -14,6 +14,10 @@
> #include "j721e_hardware.h"
> #endif
>
> +#ifdef CONFIG_SOC_K3_J721S2
> +#include "j721s2_hardware.h"
> +#endif
> +
> #ifdef CONFIG_SOC_K3_AM642
> #include "am64_hardware.h"
> #endif
> diff --git a/arch/arm/mach-k3/include/mach/j721s2_hardware.h b/arch/arm/mach-k3/include/mach/j721s2_hardware.h
> new file mode 100644
> index 000000000000..23dfe2e9e9d3
> --- /dev/null
> +++ b/arch/arm/mach-k3/include/mach/j721s2_hardware.h
> @@ -0,0 +1,60 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * K3: J721S2 SoC definitions, structures etc.
> + *
> + * (C) Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
> + */
> +#ifndef __ASM_ARCH_J721S2_HARDWARE_H
> +#define __ASM_ARCH_J721S2_HARDWARE_H
> +
> +#include <config.h>
> +#ifndef __ASSEMBLY__
> +#include <linux/bitops.h>
> +#endif
> +
> +#define CTRL_MMR0_BASE 0x00100000
> +#define CTRLMMR_MAIN_DEVSTAT (CTRL_MMR0_BASE + 0x30)
> +
> +#define MAIN_DEVSTAT_BOOT_MODE_B_MASK BIT(0)
> +#define MAIN_DEVSTAT_BOOT_MODE_B_SHIFT 0
> +#define MAIN_DEVSTAT_BKUP_BOOTMODE_MASK GENMASK(3, 1)
> +#define MAIN_DEVSTAT_BKUP_BOOTMODE_SHIFT 1
> +#define MAIN_DEVSTAT_PRIM_BOOTMODE_MMC_PORT_MASK BIT(6)
> +#define MAIN_DEVSTAT_PRIM_BOOTMODE_PORT_SHIFT 6
> +#define MAIN_DEVSTAT_BKUP_MMC_PORT_MASK BIT(7)
> +#define MAIN_DEVSTAT_BKUP_MMC_PORT_SHIFT 7
> +
> +#define WKUP_CTRL_MMR0_BASE 0x43000000
> +#define MCU_CTRL_MMR0_BASE 0x40f00000
> +
> +#define CTRLMMR_WKUP_DEVSTAT (WKUP_CTRL_MMR0_BASE + 0x30)
> +#define WKUP_DEVSTAT_PRIMARY_BOOTMODE_MASK GENMASK(5, 3)
> +#define WKUP_DEVSTAT_PRIMARY_BOOTMODE_SHIFT 3
> +#define WKUP_DEVSTAT_MCU_OMLY_MASK BIT(6)
> +#define WKUP_DEVSTAT_MCU_ONLY_SHIFT 6
> +
> +/*
> + * The CTRL_MMR0 memory space is divided into several equally-spaced
> + * partitions, so defining the partition size allows us to determine
> + * register addresses common to those partitions.
> + */
> +#define CTRL_MMR0_PARTITION_SIZE 0x4000
> +
> +/*
> + * CTRL_MMR0, WKUP_CTRL_MMR0, and MCU_CTR_MMR0 lock/kick-mechanism
> + * shared register definitions.
> + */
> +#define CTRLMMR_LOCK_KICK0 0x01008
> +#define CTRLMMR_LOCK_KICK0_UNLOCK_VAL 0x68ef3490
> +#define CTRLMMR_LOCK_KICK0_UNLOCKED_MASK BIT(0)
> +#define CTRLMMR_LOCK_KICK0_UNLOCKED_SHIFT 0
> +#define CTRLMMR_LOCK_KICK1 0x0100c
> +#define CTRLMMR_LOCK_KICK1_UNLOCK_VAL 0xd172bc5a
> +
> +/* ROM HANDOFF Structure location */
> +#define ROM_ENTENDED_BOOT_DATA_INFO 0x41cfdb00
> +
> +/* MCU SCRATCHPAD usage */
> +#define TI_SRAM_SCRATCH_BOARD_EEPROM_START CONFIG_SYS_K3_MCU_SCRATCHPAD_BASE
> +
> +#endif /* __ASM_ARCH_J721S2_HARDWARE_H */
> diff --git a/arch/arm/mach-k3/include/mach/j721s2_spl.h b/arch/arm/mach-k3/include/mach/j721s2_spl.h
> new file mode 100644
> index 000000000000..94b6c1337f73
> --- /dev/null
> +++ b/arch/arm/mach-k3/include/mach/j721s2_spl.h
> @@ -0,0 +1,46 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
> + * David Huang <d-huang at ti.com>
> + */
> +#ifndef _ASM_ARCH_J721S2_SPL_H_
> +#define _ASM_ARCH_J721S2_SPL_H_
> +
> +/* With BootMode B = 0 */
> +#include <linux/bitops.h>
> +#define BOOT_DEVICE_HYPERFLASH 0x00
> +#define BOOT_DEVICE_OSPI 0x01
> +#define BOOT_DEVICE_QSPI 0x02
> +#define BOOT_DEVICE_SPI 0x03
> +#define BOOT_DEVICE_ETHERNET 0x04
> +#define BOOT_DEVICE_I2C 0x06
> +#define BOOT_DEVICE_UART 0x07
> +#define BOOT_DEVICE_NOR BOOT_DEVICE_HYPERFLASH
> +
> +/* With BootMode B = 1 */
> +#define BOOT_DEVICE_MMC2 0x10
> +#define BOOT_DEVICE_MMC1 0x11
> +#define BOOT_DEVICE_DFU 0x12
> +#define BOOT_DEVICE_UFS 0x13
> +#define BOOT_DEVIE_GPMC 0x14
> +#define BOOT_DEVICE_PCIE 0x15
> +#define BOOT_DEVICE_XSPI 0x16
> +#define BOOT_DEVICE_RAM 0x17
> +#define BOOT_DEVICE_MMC2_2 0xFF /* Invalid value */
> +
> +/* Backup boot modes with MCU Only = 0 */
> +#define BACKUP_BOOT_DEVICE_RAM 0x0
> +#define BACKUP_BOOT_DEVICE_USB 0x1
> +#define BACKUP_BOOT_DEVICE_UART 0x3
> +#define BACKUP_BOOT_DEVICE_ETHERNET 0x4
> +#define BACKUP_BOOT_DEVICE_MMC2 0x5
> +#define BACKUP_BOOT_DEVICE_SPI 0x6
> +#define BACKUP_BOOT_DEVICE_I2C 0x7
> +
> +#define BOOT_MODE_B_SHIFT 4
> +#define BOOT_MODE_B_MASK BIT(4)
> +
> +#define K3_PRIMARY_BOOTMODE 0x0
> +#define K3_BACKUP_BOOTMODE 0x1
> +
> +#endif
> diff --git a/arch/arm/mach-k3/include/mach/spl.h b/arch/arm/mach-k3/include/mach/spl.h
> index ef1c3fb8cae6..8a6139852956 100644
> --- a/arch/arm/mach-k3/include/mach/spl.h
> +++ b/arch/arm/mach-k3/include/mach/spl.h
> @@ -14,6 +14,10 @@
> #include "j721e_spl.h"
> #endif
>
> +#ifdef CONFIG_SOC_K3_J721S2
> +#include "j721s2_spl.h"
> +#endif
> +
> #ifdef CONFIG_SOC_K3_AM642
> #include "am64_spl.h"
> #endif
> diff --git a/arch/arm/mach-k3/j721s2/Makefile b/arch/arm/mach-k3/j721s2/Makefile
> new file mode 100644
> index 000000000000..7bcd4901cd9d
> --- /dev/null
> +++ b/arch/arm/mach-k3/j721s2/Makefile
> @@ -0,0 +1,5 @@
> +# SPDX-License-Identifier: GPL-2.0+
> +#
> +# Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
> +obj-y += clk-data.o
> +obj-y += dev-data.o
> diff --git a/arch/arm/mach-k3/j721s2/clk-data.c b/arch/arm/mach-k3/j721s2/clk-data.c
> new file mode 100644
> index 000000000000..ad6bd991b707
> --- /dev/null
> +++ b/arch/arm/mach-k3/j721s2/clk-data.c
> @@ -0,0 +1,403 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * J721S2 specific clock platform data
> + *
> + * This file is auto generated. Please do not hand edit and report any issues
> + * to Dave Gerlach <d-gerlach at ti.com>.
> + *
> + * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
> + */
> +
> +#include <linux/clk-provider.h>
> +#include "k3-clk.h"
> +
> +static const char * const gluelogic_hfosc0_clkout_parents[] = {
> + "osc_19_2_mhz",
> + "osc_20_mhz",
> + "osc_24_mhz",
> + "osc_25_mhz",
> + "osc_26_mhz",
> + "osc_27_mhz",
> +};
> +
> +static const char * const mcu_ospi0_iclk_sel_out0_parents[] = {
> + "board_0_mcu_ospi0_dqs_out",
> + "fss_mcu_0_ospi_0_ospi_oclk_clk",
> +};
> +
> +static const char * const mcu_ospi1_iclk_sel_out0_parents[] = {
> + "board_0_mcu_ospi1_dqs_out",
> + "fss_mcu_0_ospi_1_ospi_oclk_clk",
> +};
> +
> +static const char * const wkup_fref_clksel_out0_parents[] = {
> + "gluelogic_hfosc0_clkout",
> + NULL,
> +};
> +
> +static const char * const main_pll_hfosc_sel_out1_parents[] = {
> + "gluelogic_hfosc0_clkout",
> + "board_0_hfosc1_clk_out",
> +};
> +
> +static const char * const k3_pll_ctrl_wrap_wkup_0_sysclkout_clk_parents[] = {
> + "wkup_fref_clksel_out0",
> + "hsdiv1_16fft_mcu_0_hsdivout0_clk",
> +};
> +
> +static const char * const mcu_ospi_ref_clk_sel_out0_parents[] = {
> + "hsdiv4_16fft_mcu_1_hsdivout4_clk",
> + "hsdiv4_16fft_mcu_2_hsdivout4_clk",
> +};
> +
> +static const char * const mcu_ospi_ref_clk_sel_out1_parents[] = {
> + "hsdiv4_16fft_mcu_1_hsdivout4_clk",
> + "hsdiv4_16fft_mcu_2_hsdivout4_clk",
> +};
> +
> +static const char * const mcu_usart_clksel_out0_parents[] = {
> + "hsdiv4_16fft_mcu_1_hsdivout3_clk",
> + "postdiv3_16fft_main_1_hsdivout5_clk",
> +};
> +
> +static const char * const wkup_i2c_mcupll_bypass_out0_parents[] = {
> + "hsdiv4_16fft_mcu_1_hsdivout3_clk",
> + "gluelogic_hfosc0_clkout",
> +};
> +
> +static const char * const main_pll_hfosc_sel_out0_parents[] = {
> + "gluelogic_hfosc0_clkout",
> + "board_0_hfosc1_clk_out",
> +};
> +
> +static const char * const main_pll_hfosc_sel_out12_parents[] = {
> + "gluelogic_hfosc0_clkout",
> + "board_0_hfosc1_clk_out",
> +};
> +
> +static const char * const main_pll_hfosc_sel_out19_parents[] = {
> + "gluelogic_hfosc0_clkout",
> + "board_0_hfosc1_clk_out",
> +};
> +
> +static const char * const main_pll_hfosc_sel_out2_parents[] = {
> + "gluelogic_hfosc0_clkout",
> + "board_0_hfosc1_clk_out",
> +};
> +
> +static const char * const main_pll_hfosc_sel_out26_0_parents[] = {
> + "gluelogic_hfosc0_clkout",
> + "board_0_hfosc1_clk_out",
> +};
> +
> +static const char * const main_pll_hfosc_sel_out3_parents[] = {
> + "gluelogic_hfosc0_clkout",
> + "board_0_hfosc1_clk_out",
> +};
> +
> +static const char * const main_pll_hfosc_sel_out7_parents[] = {
> + "gluelogic_hfosc0_clkout",
> + "board_0_hfosc1_clk_out",
> +};
> +
> +static const char * const main_pll_hfosc_sel_out8_parents[] = {
> + "gluelogic_hfosc0_clkout",
> + "board_0_hfosc1_clk_out",
> +};
> +
> +static const char * const usb0_refclk_sel_out0_parents[] = {
> + "gluelogic_hfosc0_clkout",
> + "board_0_hfosc1_clk_out",
> +};
> +
> +static const char * const emmcsd1_lb_clksel_out0_parents[] = {
> + "board_0_mmc1_clklb_out",
> + "board_0_mmc1_clk_out",
> +};
> +
> +static const char * const mcu_clkout_mux_out0_parents[] = {
> + "hsdiv4_16fft_mcu_2_hsdivout0_clk",
> + "hsdiv4_16fft_mcu_2_hsdivout0_clk",
> +};
> +
> +static const char * const k3_pll_ctrl_wrap_main_0_sysclkout_clk_parents[] = {
> + "main_pll_hfosc_sel_out0",
> + "hsdiv4_16fft_main_0_hsdivout0_clk",
> +};
> +
> +static const char * const dpi0_ext_clksel_out0_parents[] = {
> + "hsdiv1_16fft_main_19_hsdivout0_clk",
> + "board_0_vout0_extpclkin_out",
> +};
> +
> +static const char * const emmcsd_refclk_sel_out0_parents[] = {
> + "hsdiv4_16fft_main_0_hsdivout2_clk",
> + "hsdiv4_16fft_main_1_hsdivout2_clk",
> + "hsdiv4_16fft_main_2_hsdivout2_clk",
> + "hsdiv4_16fft_main_3_hsdivout2_clk",
> +};
> +
> +static const char * const emmcsd_refclk_sel_out1_parents[] = {
> + "hsdiv4_16fft_main_0_hsdivout2_clk",
> + "hsdiv4_16fft_main_1_hsdivout2_clk",
> + "hsdiv4_16fft_main_2_hsdivout2_clk",
> + "hsdiv4_16fft_main_3_hsdivout2_clk",
> +};
> +
> +static const char * const gtc_clk_mux_out0_parents[] = {
> + "hsdiv4_16fft_main_3_hsdivout1_clk",
> + "postdiv3_16fft_main_0_hsdivout6_clk",
> + "board_0_mcu_cpts0_rft_clk_out",
> + "board_0_cpts0_rft_clk_out",
> + "board_0_mcu_ext_refclk0_out",
> + "board_0_ext_refclk1_out",
> + NULL,
> + NULL,
> + NULL,
> + NULL,
> + NULL,
> + NULL,
> + NULL,
> + NULL,
> + "hsdiv4_16fft_mcu_2_hsdivout1_clk",
> + "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk",
> +};
> +
> +static const struct clk_data clk_list[] = {
> + CLK_FIXED_RATE("osc_27_mhz", 27000000, 0),
> + CLK_FIXED_RATE("osc_26_mhz", 26000000, 0),
> + CLK_FIXED_RATE("osc_25_mhz", 25000000, 0),
> + CLK_FIXED_RATE("osc_24_mhz", 24000000, 0),
> + CLK_FIXED_RATE("osc_20_mhz", 20000000, 0),
> + CLK_FIXED_RATE("osc_19_2_mhz", 19200000, 0),
> + CLK_MUX("gluelogic_hfosc0_clkout", gluelogic_hfosc0_clkout_parents, 6, 0x43000030, 0, 3, 0),
> + CLK_FIXED_RATE("board_0_hfosc1_clk_out", 0, 0),
> + CLK_FIXED_RATE("board_0_mcu_ospi0_dqs_out", 0, 0),
> + CLK_FIXED_RATE("board_0_mcu_ospi1_dqs_out", 0, 0),
> + CLK_FIXED_RATE("board_0_wkup_i2c0_scl_out", 0, 0),
> + CLK_FIXED_RATE("fss_mcu_0_hyperbus1p0_0_hpb_out_clk_n", 0, 0),
> + CLK_FIXED_RATE("fss_mcu_0_hyperbus1p0_0_hpb_out_clk_p", 0, 0),
> + CLK_FIXED_RATE("fss_mcu_0_ospi_0_ospi_oclk_clk", 0, 0),
> + CLK_FIXED_RATE("fss_mcu_0_ospi_1_ospi_oclk_clk", 0, 0),
> + CLK_MUX("mcu_ospi0_iclk_sel_out0", mcu_ospi0_iclk_sel_out0_parents, 2, 0x40f08030, 4, 1, 0),
> + CLK_MUX("mcu_ospi1_iclk_sel_out0", mcu_ospi1_iclk_sel_out0_parents, 2, 0x40f08034, 4, 1, 0),
> + CLK_FIXED_RATE("mshsi2c_wkup_0_porscl", 0, 0),
> + CLK_MUX("wkup_fref_clksel_out0", wkup_fref_clksel_out0_parents, 2, 0x43008050, 8, 1, 0),
> + CLK_MUX("main_pll_hfosc_sel_out1", main_pll_hfosc_sel_out1_parents, 2, 0x43008084, 0, 1, 0),
> + CLK_PLL_DEFFREQ("pllfracf2_ssmod_16fft_main_1_foutvcop_clk", "main_pll_hfosc_sel_out1", 0x681000, 0, 1920000000),
> + CLK_DIV("pllfracf2_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", "pllfracf2_ssmod_16fft_main_1_foutvcop_clk", 0x681038, 16, 3, 0, CLK_DIVIDER_ONE_BASED),
> + CLK_DIV("pllfracf2_ssmod_16fft_main_1_foutpostdiv_clk", "pllfracf2_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", 0x681038, 24, 3, 0, CLK_DIVIDER_ONE_BASED),
> + CLK_PLL("pllfracf2_ssmod_16fft_mcu_0_foutvcop_clk", "wkup_fref_clksel_out0", 0x40d00000, 0),
> + CLK_PLL_DEFFREQ("pllfracf2_ssmod_16fft_mcu_1_foutvcop_clk", "wkup_fref_clksel_out0", 0x40d01000, 0, 2400000000),
> + CLK_PLL_DEFFREQ("pllfracf2_ssmod_16fft_mcu_2_foutvcop_clk", "wkup_fref_clksel_out0", 0x40d02000, 0, 2000000000),
> + CLK_DIV("postdiv3_16fft_main_1_hsdivout5_clk", "pllfracf2_ssmod_16fft_main_1_foutpostdiv_clk", 0x681094, 0, 7, 0, 0),
> + CLK_DIV("hsdiv1_16fft_mcu_0_hsdivout0_clk", "pllfracf2_ssmod_16fft_mcu_0_foutvcop_clk", 0x40d00080, 0, 7, 0, 0),
> + CLK_DIV("hsdiv4_16fft_mcu_1_hsdivout3_clk", "pllfracf2_ssmod_16fft_mcu_1_foutvcop_clk", 0x40d0108c, 0, 7, 0, 0),
> + CLK_DIV("hsdiv4_16fft_mcu_1_hsdivout4_clk", "pllfracf2_ssmod_16fft_mcu_1_foutvcop_clk", 0x40d01090, 0, 7, 0, 0),
> + CLK_DIV_DEFFREQ("hsdiv4_16fft_mcu_2_hsdivout4_clk", "pllfracf2_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02090, 0, 7, 0, 0, 166666666),
> + CLK_MUX_PLLCTRL("k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", k3_pll_ctrl_wrap_wkup_0_sysclkout_clk_parents, 2, 0x42010000, 0),
> + CLK_DIV("k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk", "k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", 0x42010118, 0, 5, 0, 0),
> + CLK_MUX("mcu_ospi_ref_clk_sel_out0", mcu_ospi_ref_clk_sel_out0_parents, 2, 0x40f08030, 0, 1, 0),
> + CLK_MUX("mcu_ospi_ref_clk_sel_out1", mcu_ospi_ref_clk_sel_out1_parents, 2, 0x40f08034, 0, 1, 0),
> + CLK_MUX("mcu_usart_clksel_out0", mcu_usart_clksel_out0_parents, 2, 0x40f081c0, 0, 1, 0),
> + CLK_MUX("wkup_i2c_mcupll_bypass_out0", wkup_i2c_mcupll_bypass_out0_parents, 2, 0x43008060, 0, 1, 0),
> + CLK_MUX("main_pll_hfosc_sel_out0", main_pll_hfosc_sel_out0_parents, 2, 0x43008080, 0, 1, 0),
> + CLK_MUX("main_pll_hfosc_sel_out12", main_pll_hfosc_sel_out12_parents, 2, 0x430080b0, 0, 1, 0),
> + CLK_MUX("main_pll_hfosc_sel_out19", main_pll_hfosc_sel_out19_parents, 2, 0x430080cc, 0, 1, 0),
> + CLK_MUX("main_pll_hfosc_sel_out2", main_pll_hfosc_sel_out2_parents, 2, 0x43008088, 0, 1, 0),
> + CLK_MUX("main_pll_hfosc_sel_out26_0", main_pll_hfosc_sel_out26_0_parents, 2, 0x430080e8, 0, 1, 0),
> + CLK_MUX("main_pll_hfosc_sel_out3", main_pll_hfosc_sel_out3_parents, 2, 0x4300808c, 0, 1, 0),
> + CLK_MUX("main_pll_hfosc_sel_out7", main_pll_hfosc_sel_out7_parents, 2, 0x4300809c, 0, 1, 0),
> + CLK_MUX("main_pll_hfosc_sel_out8", main_pll_hfosc_sel_out8_parents, 2, 0x430080a0, 0, 1, 0),
> + CLK_MUX("usb0_refclk_sel_out0", usb0_refclk_sel_out0_parents, 2, 0x1080e0, 0, 1, 0),
> + CLK_FIXED_RATE("board_0_cpts0_rft_clk_out", 0, 0),
> + CLK_FIXED_RATE("board_0_ddr0_ckn_out", 0, 0),
> + CLK_FIXED_RATE("board_0_ddr0_ckp_out", 0, 0),
> + CLK_FIXED_RATE("board_0_ddr1_ckn_out", 0, 0),
> + CLK_FIXED_RATE("board_0_ddr1_ckp_out", 0, 0),
> + CLK_FIXED_RATE("board_0_ext_refclk1_out", 0, 0),
> + CLK_FIXED_RATE("board_0_mcu_cpts0_rft_clk_out", 0, 0),
> + CLK_FIXED_RATE("board_0_mcu_ext_refclk0_out", 0, 0),
> + CLK_FIXED_RATE("board_0_mmc1_clklb_out", 0, 0),
> + CLK_FIXED_RATE("board_0_mmc1_clk_out", 0, 0),
> + CLK_FIXED_RATE("board_0_vout0_extpclkin_out", 0, 0),
> + CLK_FIXED_RATE("emmc8ss_16ffc_main_0_emmcss_io_clk", 0, 0),
> + CLK_FIXED_RATE("emmcsd4ss_main_0_emmcsdss_io_clk_o", 0, 0),
> + CLK_DIV_DEFFREQ("hsdiv4_16fft_main_1_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_1_foutvcop_clk", 0x681080, 0, 7, 0, 0, 192000000),
> + CLK_DIV("hsdiv4_16fft_main_1_hsdivout2_clk", "pllfracf2_ssmod_16fft_main_1_foutvcop_clk", 0x681088, 0, 7, 0, 0),
> + CLK_DIV("hsdiv4_16fft_mcu_2_hsdivout0_clk", "pllfracf2_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02080, 0, 7, 0, 0),
> + CLK_DIV("hsdiv4_16fft_mcu_2_hsdivout1_clk", "pllfracf2_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02084, 0, 7, 0, 0),
> + CLK_FIXED_RATE("j7am_ddr_ew_wrap_dv_wrap_main_0_ddrss_io_ck", 0, 0),
> + CLK_FIXED_RATE("j7am_ddr_ew_wrap_dv_wrap_main_0_ddrss_io_ck_n", 0, 0),
> + CLK_FIXED_RATE("j7am_ddr_ew_wrap_dv_wrap_main_1_ddrss_io_ck", 0, 0),
> + CLK_FIXED_RATE("j7am_ddr_ew_wrap_dv_wrap_main_1_ddrss_io_ck_n", 0, 0),
> + CLK_PLL("pllfracf2_ssmod_16fft_main_0_foutvcop_clk", "main_pll_hfosc_sel_out0", 0x680000, 0),
> + CLK_DIV("pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x680038, 16, 3, 0, CLK_DIVIDER_ONE_BASED),
> + CLK_DIV("pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk", "pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", 0x680038, 24, 3, 0, CLK_DIVIDER_ONE_BASED),
> + CLK_PLL("pllfracf2_ssmod_16fft_main_12_foutvcop_clk", "main_pll_hfosc_sel_out12", 0x68c000, 0),
> + CLK_PLL("pllfracf2_ssmod_16fft_main_19_foutvcop_clk", "main_pll_hfosc_sel_out19", 0x693000, 0),
> + CLK_PLL("pllfracf2_ssmod_16fft_main_2_foutvcop_clk", "main_pll_hfosc_sel_out2", 0x682000, 0),
> + CLK_PLL("pllfracf2_ssmod_16fft_main_26_foutvcop_clk", "main_pll_hfosc_sel_out26_0", 0x69a000, 0),
> + CLK_PLL("pllfracf2_ssmod_16fft_main_3_foutvcop_clk", "main_pll_hfosc_sel_out3", 0x683000, 0),
> + CLK_PLL("pllfracf2_ssmod_16fft_main_7_foutvcop_clk", "main_pll_hfosc_sel_out7", 0x687000, 0),
> + CLK_PLL("pllfracf2_ssmod_16fft_main_8_foutvcop_clk", "main_pll_hfosc_sel_out8", 0x688000, 0),
> + CLK_DIV("postdiv3_16fft_main_0_hsdivout6_clk", "pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk", 0x680098, 0, 7, 0, 0),
> + CLK_DIV("postdiv3_16fft_main_0_hsdivout8_clk", "pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk", 0x6800a0, 0, 7, 0, 0),
> + CLK_DIV("postdiv3_16fft_main_1_hsdivout7_clk", "pllfracf2_ssmod_16fft_main_1_foutpostdiv_clk", 0x68109c, 0, 7, 0, 0),
> + CLK_MUX("emmcsd1_lb_clksel_out0", emmcsd1_lb_clksel_out0_parents, 2, 0x1080b4, 16, 1, 0),
> + CLK_MUX("mcu_clkout_mux_out0", mcu_clkout_mux_out0_parents, 2, 0x40f08010, 0, 1, 0),
> + CLK_DIV_DEFFREQ("usart_programmable_clock_divider_out0", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081c0, 0, 2, 0, 0, 48000000),
> + CLK_DIV("usart_programmable_clock_divider_out8", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081e0, 0, 2, 0, 0),
> + CLK_DIV("hsdiv0_16fft_main_12_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_12_foutvcop_clk", 0x68c080, 0, 7, 0, 0),
> + CLK_DIV("hsdiv0_16fft_main_26_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_26_foutvcop_clk", 0x69a080, 0, 7, 0, 0),
> + CLK_DIV("hsdiv0_16fft_main_7_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_7_foutvcop_clk", 0x687080, 0, 7, 0, 0),
> + CLK_DIV("hsdiv0_16fft_main_8_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_8_foutvcop_clk", 0x688080, 0, 7, 0, 0),
> + CLK_DIV("hsdiv1_16fft_main_19_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_19_foutvcop_clk", 0x693080, 0, 7, 0, 0),
> + CLK_DIV("hsdiv4_16fft_main_0_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x680080, 0, 7, 0, 0),
> + CLK_DIV("hsdiv4_16fft_main_0_hsdivout2_clk", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x680088, 0, 7, 0, 0),
> + CLK_DIV("hsdiv4_16fft_main_0_hsdivout3_clk", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x68008c, 0, 7, 0, 0),
> + CLK_DIV("hsdiv4_16fft_main_0_hsdivout4_clk", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x680090, 0, 7, 0, 0),
> + CLK_DIV("hsdiv4_16fft_main_2_hsdivout2_clk", "pllfracf2_ssmod_16fft_main_2_foutvcop_clk", 0x682088, 0, 7, 0, 0),
> + CLK_DIV("hsdiv4_16fft_main_3_hsdivout1_clk", "pllfracf2_ssmod_16fft_main_3_foutvcop_clk", 0x683084, 0, 7, 0, 0),
> + CLK_DIV("hsdiv4_16fft_main_3_hsdivout2_clk", "pllfracf2_ssmod_16fft_main_3_foutvcop_clk", 0x683088, 0, 7, 0, 0),
> + CLK_MUX_PLLCTRL("k3_pll_ctrl_wrap_main_0_sysclkout_clk", k3_pll_ctrl_wrap_main_0_sysclkout_clk_parents, 2, 0x410000, 0),
> + CLK_DIV("k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk", "k3_pll_ctrl_wrap_main_0_sysclkout_clk", 0x410118, 0, 5, 0, 0),
> + CLK_MUX("dpi0_ext_clksel_out0", dpi0_ext_clksel_out0_parents, 2, 0x108300, 0, 1, 0),
> + CLK_MUX("emmcsd_refclk_sel_out0", emmcsd_refclk_sel_out0_parents, 4, 0x1080b0, 0, 2, 0),
> + CLK_MUX("emmcsd_refclk_sel_out1", emmcsd_refclk_sel_out1_parents, 4, 0x1080b4, 0, 2, 0),
> + CLK_MUX("gtc_clk_mux_out0", gtc_clk_mux_out0_parents, 16, 0x108030, 0, 4, 0),
> + CLK_DIV("k3_pll_ctrl_wrap_main_0_chip_div24_clk_clk", "k3_pll_ctrl_wrap_main_0_sysclkout_clk", 0x41011c, 0, 5, 0, 0),
> + CLK_DIV("k3_pll_ctrl_wrap_wkup_0_chip_div24_clk_clk", "k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", 0x4201011c, 0, 5, 0, 0),
> +};
> +
> +static const struct dev_clk soc_dev_clk_data[] = {
> + DEV_CLK(4, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"),
> + DEV_CLK(4, 1, "hsdiv0_16fft_main_7_hsdivout0_clk"),
> + DEV_CLK(4, 2, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
> + DEV_CLK(43, 0, "postdiv3_16fft_main_0_hsdivout8_clk"),
> + DEV_CLK(43, 1, "hsdiv4_16fft_main_0_hsdivout3_clk"),
> + DEV_CLK(43, 2, "gluelogic_hfosc0_clkout"),
> + DEV_CLK(43, 3, "board_0_hfosc1_clk_out"),
> + DEV_CLK(43, 5, "hsdiv4_16fft_main_0_hsdivout2_clk"),
> + DEV_CLK(43, 6, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
> + DEV_CLK(43, 7, "board_0_hfosc1_clk_out"),
> + DEV_CLK(43, 9, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
> + DEV_CLK(43, 10, "hsdiv4_16fft_main_0_hsdivout4_clk"),
> + DEV_CLK(43, 11, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
> + DEV_CLK(43, 12, "gluelogic_hfosc0_clkout"),
> + DEV_CLK(61, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
> + DEV_CLK(61, 1, "gtc_clk_mux_out0"),
> + DEV_CLK(61, 2, "hsdiv4_16fft_main_3_hsdivout1_clk"),
> + DEV_CLK(61, 3, "postdiv3_16fft_main_0_hsdivout6_clk"),
> + DEV_CLK(61, 4, "board_0_mcu_cpts0_rft_clk_out"),
> + DEV_CLK(61, 5, "board_0_cpts0_rft_clk_out"),
> + DEV_CLK(61, 6, "board_0_mcu_ext_refclk0_out"),
> + DEV_CLK(61, 7, "board_0_ext_refclk1_out"),
> + DEV_CLK(61, 16, "hsdiv4_16fft_mcu_2_hsdivout1_clk"),
> + DEV_CLK(61, 17, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
> + DEV_CLK(98, 1, "emmcsd_refclk_sel_out0"),
> + DEV_CLK(98, 2, "hsdiv4_16fft_main_0_hsdivout2_clk"),
> + DEV_CLK(98, 3, "hsdiv4_16fft_main_1_hsdivout2_clk"),
> + DEV_CLK(98, 4, "hsdiv4_16fft_main_2_hsdivout2_clk"),
> + DEV_CLK(98, 5, "hsdiv4_16fft_main_3_hsdivout2_clk"),
> + DEV_CLK(98, 6, "emmcsd1_lb_clksel_out0"),
> + DEV_CLK(98, 7, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
> + DEV_CLK(99, 1, "emmcsd_refclk_sel_out1"),
> + DEV_CLK(99, 2, "hsdiv4_16fft_main_0_hsdivout2_clk"),
> + DEV_CLK(99, 3, "hsdiv4_16fft_main_1_hsdivout2_clk"),
> + DEV_CLK(99, 4, "hsdiv4_16fft_main_2_hsdivout2_clk"),
> + DEV_CLK(99, 5, "hsdiv4_16fft_main_3_hsdivout2_clk"),
> + DEV_CLK(99, 7, "emmcsd4ss_main_0_emmcsdss_io_clk_o"),
> + DEV_CLK(99, 8, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
> + DEV_CLK(108, 1, "hsdiv4_16fft_mcu_2_hsdivout4_clk"),
> + DEV_CLK(108, 2, "hsdiv4_16fft_mcu_2_hsdivout4_clk"),
> + DEV_CLK(108, 3, "hsdiv4_16fft_mcu_2_hsdivout4_clk"),
> + DEV_CLK(108, 6, "hsdiv4_16fft_mcu_2_hsdivout4_clk"),
> + DEV_CLK(108, 11, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
> + DEV_CLK(109, 0, "mcu_ospi0_iclk_sel_out0"),
> + DEV_CLK(109, 1, "board_0_mcu_ospi0_dqs_out"),
> + DEV_CLK(109, 2, "fss_mcu_0_ospi_0_ospi_oclk_clk"),
> + DEV_CLK(109, 3, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
> + DEV_CLK(109, 5, "mcu_ospi_ref_clk_sel_out0"),
> + DEV_CLK(109, 6, "hsdiv4_16fft_mcu_1_hsdivout4_clk"),
> + DEV_CLK(109, 7, "hsdiv4_16fft_mcu_2_hsdivout4_clk"),
> + DEV_CLK(109, 8, "board_0_mcu_ospi0_dqs_out"),
> + DEV_CLK(109, 9, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
> + DEV_CLK(110, 0, "mcu_ospi1_iclk_sel_out0"),
> + DEV_CLK(110, 1, "board_0_mcu_ospi1_dqs_out"),
> + DEV_CLK(110, 2, "fss_mcu_0_ospi_1_ospi_oclk_clk"),
> + DEV_CLK(110, 3, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
> + DEV_CLK(110, 5, "mcu_ospi_ref_clk_sel_out1"),
> + DEV_CLK(110, 6, "hsdiv4_16fft_mcu_1_hsdivout4_clk"),
> + DEV_CLK(110, 7, "hsdiv4_16fft_mcu_2_hsdivout4_clk"),
> + DEV_CLK(110, 8, "board_0_mcu_ospi1_dqs_out"),
> + DEV_CLK(110, 9, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
> + DEV_CLK(115, 0, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
> + DEV_CLK(126, 0, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
> + DEV_CLK(126, 1, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
> + DEV_CLK(138, 0, "hsdiv0_16fft_main_12_hsdivout0_clk"),
> + DEV_CLK(138, 1, "hsdiv0_16fft_main_7_hsdivout0_clk"),
> + DEV_CLK(138, 2, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
> + DEV_CLK(138, 3, "board_0_ddr0_ckn_out"),
> + DEV_CLK(138, 5, "board_0_ddr0_ckp_out"),
> + DEV_CLK(138, 7, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
> + DEV_CLK(139, 0, "hsdiv0_16fft_main_26_hsdivout0_clk"),
> + DEV_CLK(139, 1, "hsdiv0_16fft_main_7_hsdivout0_clk"),
> + DEV_CLK(139, 2, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
> + DEV_CLK(139, 3, "board_0_ddr1_ckn_out"),
> + DEV_CLK(139, 5, "board_0_ddr1_ckp_out"),
> + DEV_CLK(139, 7, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
> + DEV_CLK(143, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
> + DEV_CLK(143, 1, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
> + DEV_CLK(146, 2, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
> + DEV_CLK(146, 3, "usart_programmable_clock_divider_out0"),
> + DEV_CLK(149, 2, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
> + DEV_CLK(149, 3, "mcu_usart_clksel_out0"),
> + DEV_CLK(149, 4, "hsdiv4_16fft_mcu_1_hsdivout3_clk"),
> + DEV_CLK(149, 5, "postdiv3_16fft_main_1_hsdivout5_clk"),
> + DEV_CLK(157, 9, "emmcsd4ss_main_0_emmcsdss_io_clk_o"),
> + DEV_CLK(157, 103, "fss_mcu_0_ospi_0_ospi_oclk_clk"),
> + DEV_CLK(157, 104, "j7am_ddr_ew_wrap_dv_wrap_main_0_ddrss_io_ck"),
> + DEV_CLK(157, 111, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
> + DEV_CLK(157, 174, "j7am_ddr_ew_wrap_dv_wrap_main_1_ddrss_io_ck"),
> + DEV_CLK(157, 177, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
> + DEV_CLK(157, 179, "fss_mcu_0_ospi_0_ospi_oclk_clk"),
> + DEV_CLK(157, 182, "mshsi2c_wkup_0_porscl"),
> + DEV_CLK(157, 187, "fss_mcu_0_ospi_1_ospi_oclk_clk"),
> + DEV_CLK(157, 194, "emmcsd4ss_main_0_emmcsdss_io_clk_o"),
> + DEV_CLK(157, 197, "j7am_ddr_ew_wrap_dv_wrap_main_0_ddrss_io_ck_n"),
> + DEV_CLK(157, 208, "j7am_ddr_ew_wrap_dv_wrap_main_1_ddrss_io_ck_n"),
> + DEV_CLK(157, 214, "fss_mcu_0_hyperbus1p0_0_hpb_out_clk_p"),
> + DEV_CLK(157, 221, "mcu_clkout_mux_out0"),
> + DEV_CLK(157, 222, "hsdiv4_16fft_mcu_2_hsdivout0_clk"),
> + DEV_CLK(157, 223, "hsdiv4_16fft_mcu_2_hsdivout0_clk"),
> + DEV_CLK(157, 225, "emmc8ss_16ffc_main_0_emmcss_io_clk"),
> + DEV_CLK(157, 231, "fss_mcu_0_hyperbus1p0_0_hpb_out_clk_n"),
> + DEV_CLK(157, 352, "dpi0_ext_clksel_out0"),
> + DEV_CLK(180, 0, "gluelogic_hfosc0_clkout"),
> + DEV_CLK(180, 2, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
> + DEV_CLK(202, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"),
> + DEV_CLK(203, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"),
> + DEV_CLK(223, 1, "wkup_i2c_mcupll_bypass_out0"),
> + DEV_CLK(223, 2, "hsdiv4_16fft_mcu_1_hsdivout3_clk"),
> + DEV_CLK(223, 3, "gluelogic_hfosc0_clkout"),
> + DEV_CLK(223, 4, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
> + DEV_CLK(223, 5, "board_0_wkup_i2c0_scl_out"),
> + DEV_CLK(357, 2, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
> + DEV_CLK(357, 3, "usart_programmable_clock_divider_out8"),
> + DEV_CLK(360, 4, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
> + DEV_CLK(360, 13, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
> + DEV_CLK(360, 15, "postdiv3_16fft_main_1_hsdivout7_clk"),
> + DEV_CLK(360, 16, "usb0_refclk_sel_out0"),
> + DEV_CLK(360, 17, "gluelogic_hfosc0_clkout"),
> + DEV_CLK(360, 18, "board_0_hfosc1_clk_out"),
> + DEV_CLK(360, 22, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
> + DEV_CLK(360, 23, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
> +};
> +
> +const struct ti_k3_clk_platdata j721s2_clk_platdata = {
> + .clk_list = clk_list,
> + .clk_list_cnt = 104,
> + .soc_dev_clk_data = soc_dev_clk_data,
> + .soc_dev_clk_data_cnt = 122,
> +};
> diff --git a/arch/arm/mach-k3/j721s2/dev-data.c b/arch/arm/mach-k3/j721s2/dev-data.c
> new file mode 100644
> index 000000000000..e36f1edb7866
> --- /dev/null
> +++ b/arch/arm/mach-k3/j721s2/dev-data.c
> @@ -0,0 +1,85 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * J721S2 specific device platform data
> + *
> + * This file is auto generated. Please do not hand edit and report any issues
> + * to Dave Gerlach <d-gerlach at ti.com>.
> + *
> + * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
> + */
> +
> +#include "k3-dev.h"
> +
> +static struct ti_psc soc_psc_list[] = {
> + [0] = PSC(0, 0x42000000),
> + [1] = PSC(1, 0x00400000),
> +};
> +
> +static struct ti_pd soc_pd_list[] = {
> + [0] = PSC_PD(0, &soc_psc_list[0], NULL),
> + [1] = PSC_PD(0, &soc_psc_list[1], NULL),
> + [2] = PSC_PD(1, &soc_psc_list[1], &soc_pd_list[1]),
> + [3] = PSC_PD(14, &soc_psc_list[1], NULL),
> + [4] = PSC_PD(15, &soc_psc_list[1], &soc_pd_list[3]),
> + [5] = PSC_PD(16, &soc_psc_list[1], &soc_pd_list[3]),
> +};
> +
> +static struct ti_lpsc soc_lpsc_list[] = {
> + [0] = PSC_LPSC(0, &soc_psc_list[0], &soc_pd_list[0], NULL),
> + [1] = PSC_LPSC(3, &soc_psc_list[0], &soc_pd_list[0], NULL),
> + [2] = PSC_LPSC(10, &soc_psc_list[0], &soc_pd_list[0], NULL),
> + [3] = PSC_LPSC(11, &soc_psc_list[0], &soc_pd_list[0], NULL),
> + [4] = PSC_LPSC(12, &soc_psc_list[0], &soc_pd_list[0], NULL),
> + [5] = PSC_LPSC(0, &soc_psc_list[1], &soc_pd_list[1], NULL),
> + [6] = PSC_LPSC(9, &soc_psc_list[1], &soc_pd_list[1], &soc_lpsc_list[2]),
> + [7] = PSC_LPSC(14, &soc_psc_list[1], &soc_pd_list[1], &soc_lpsc_list[8]),
> + [8] = PSC_LPSC(15, &soc_psc_list[1], &soc_pd_list[1], NULL),
> + [9] = PSC_LPSC(16, &soc_psc_list[1], &soc_pd_list[1], &soc_lpsc_list[10]),
> + [10] = PSC_LPSC(17, &soc_psc_list[1], &soc_pd_list[1], NULL),
> + [11] = PSC_LPSC(20, &soc_psc_list[1], &soc_pd_list[1], &soc_lpsc_list[4]),
> + [12] = PSC_LPSC(23, &soc_psc_list[1], &soc_pd_list[1], &soc_lpsc_list[4]),
> + [13] = PSC_LPSC(25, &soc_psc_list[1], &soc_pd_list[1], &soc_lpsc_list[4]),
> + [14] = PSC_LPSC(43, &soc_psc_list[1], &soc_pd_list[2], NULL),
> + [15] = PSC_LPSC(45, &soc_psc_list[1], &soc_pd_list[2], NULL),
> + [16] = PSC_LPSC(78, &soc_psc_list[1], &soc_pd_list[3], NULL),
> + [17] = PSC_LPSC(80, &soc_psc_list[1], &soc_pd_list[4], &soc_lpsc_list[16]),
> + [18] = PSC_LPSC(81, &soc_psc_list[1], &soc_pd_list[5], &soc_lpsc_list[16]),
> +};
> +
> +static struct ti_dev soc_dev_list[] = {
> + PSC_DEV(108, &soc_lpsc_list[0]),
> + PSC_DEV(109, &soc_lpsc_list[0]),
> + PSC_DEV(110, &soc_lpsc_list[0]),
> + PSC_DEV(180, &soc_lpsc_list[0]),
> + PSC_DEV(149, &soc_lpsc_list[0]),
> + PSC_DEV(115, &soc_lpsc_list[1]),
> + PSC_DEV(223, &soc_lpsc_list[1]),
> + PSC_DEV(109, &soc_lpsc_list[2]),
> + PSC_DEV(110, &soc_lpsc_list[3]),
> + PSC_DEV(108, &soc_lpsc_list[4]),
> + PSC_DEV(43, &soc_lpsc_list[5]),
> + PSC_DEV(61, &soc_lpsc_list[6]),
> + PSC_DEV(96, &soc_lpsc_list[7]),
> + PSC_DEV(138, &soc_lpsc_list[8]),
> + PSC_DEV(97, &soc_lpsc_list[9]),
> + PSC_DEV(139, &soc_lpsc_list[10]),
> + PSC_DEV(360, &soc_lpsc_list[11]),
> + PSC_DEV(99, &soc_lpsc_list[12]),
> + PSC_DEV(98, &soc_lpsc_list[13]),
> + PSC_DEV(146, &soc_lpsc_list[14]),
> + PSC_DEV(357, &soc_lpsc_list[15]),
> + PSC_DEV(4, &soc_lpsc_list[16]),
> + PSC_DEV(202, &soc_lpsc_list[17]),
> + PSC_DEV(203, &soc_lpsc_list[18]),
> +};
> +
> +const struct ti_k3_pd_platdata j721s2_pd_platdata = {
> + .psc = soc_psc_list,
> + .pd = soc_pd_list,
> + .lpsc = soc_lpsc_list,
> + .devs = soc_dev_list,
> + .num_psc = 2,
> + .num_pd = 6,
> + .num_lpsc = 19,
> + .num_devs = 24,
> +};
> diff --git a/arch/arm/mach-k3/j721s2_init.c b/arch/arm/mach-k3/j721s2_init.c
> new file mode 100644
> index 000000000000..58a86541b79f
> --- /dev/null
> +++ b/arch/arm/mach-k3/j721s2_init.c
> @@ -0,0 +1,312 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * J721E: SoC specific initialization
> + *
> + * Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
> + * David Huang <d-huang at ti.com>
> + */
> +
> +#include <common.h>
> +#include <init.h>
> +#include <spl.h>
> +#include <asm/io.h>
> +#include <asm/armv7_mpu.h>
> +#include <asm/arch/hardware.h>
> +#include <asm/arch/sysfw-loader.h>
> +#include "common.h"
> +#include <asm/arch/sys_proto.h>
> +#include <linux/soc/ti/ti_sci_protocol.h>
> +#include <dm.h>
> +#include <dm/uclass-internal.h>
> +#include <dm/pinctrl.h>
> +#include <mmc.h>
> +#include <remoteproc.h>
> +
> +#ifdef CONFIG_SPL_BUILD
> +
> +static void ctrl_mmr_unlock(void)
> +{
> + /* Unlock all WKUP_CTRL_MMR0 module registers */
> + mmr_unlock(WKUP_CTRL_MMR0_BASE, 0);
> + mmr_unlock(WKUP_CTRL_MMR0_BASE, 1);
> + mmr_unlock(WKUP_CTRL_MMR0_BASE, 2);
> + mmr_unlock(WKUP_CTRL_MMR0_BASE, 3);
> + mmr_unlock(WKUP_CTRL_MMR0_BASE, 4);
> + mmr_unlock(WKUP_CTRL_MMR0_BASE, 6);
> + mmr_unlock(WKUP_CTRL_MMR0_BASE, 7);
> +
> + /* Unlock all MCU_CTRL_MMR0 module registers */
> + mmr_unlock(MCU_CTRL_MMR0_BASE, 0);
> + mmr_unlock(MCU_CTRL_MMR0_BASE, 1);
> + mmr_unlock(MCU_CTRL_MMR0_BASE, 2);
> + mmr_unlock(MCU_CTRL_MMR0_BASE, 3);
> + mmr_unlock(MCU_CTRL_MMR0_BASE, 4);
> +
> + /* Unlock all CTRL_MMR0 module registers */
> + mmr_unlock(CTRL_MMR0_BASE, 0);
> + mmr_unlock(CTRL_MMR0_BASE, 1);
> + mmr_unlock(CTRL_MMR0_BASE, 2);
> + mmr_unlock(CTRL_MMR0_BASE, 3);
> + mmr_unlock(CTRL_MMR0_BASE, 5);
> + mmr_unlock(CTRL_MMR0_BASE, 7);
> +}
> +
> +void k3_mmc_stop_clock(void)
> +{
> + if (IS_ENABLED(CONFIG_K3_LOAD_SYSFW)) {
> + if (spl_boot_device() == BOOT_DEVICE_MMC1) {
> + struct mmc *mmc = find_mmc_device(0);
> +
> + if (!mmc)
> + return;
> +
> + mmc->saved_clock = mmc->clock;
> + mmc_set_clock(mmc, 0, true);
> + }
> + }
> +}
> +
> +void k3_mmc_restart_clock(void)
> +{
> + if (IS_ENABLED(CONFIG_K3_LOAD_SYSFW)) {
> + if (spl_boot_device() == BOOT_DEVICE_MMC1) {
> + struct mmc *mmc = find_mmc_device(0);
> +
> + if (!mmc)
> + return;
> +
> + mmc_set_clock(mmc, mmc->saved_clock, false);
> + }
> + }
> +}
> +
> +/*
> + * This uninitialized global variable would normal end up in the .bss section,
> + * but the .bss is cleared between writing and reading this variable, so move
> + * it to the .data section.
> + */
> +u32 bootindex __attribute__((section(".data")));
> +static struct rom_extended_boot_data bootdata __section(".data");
> +
> +static void store_boot_info_from_rom(void)
> +{
> + bootindex = *(u32 *)(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX);
> + memcpy(&bootdata, (uintptr_t *)ROM_ENTENDED_BOOT_DATA_INFO,
> + sizeof(struct rom_extended_boot_data));
> +}
> +
> +void board_init_f(ulong dummy)
> +{
> + struct udevice *dev;
> + int ret;
> + /*
> + * Cannot delay this further as there is a chance that
> + * K3_BOOT_PARAM_TABLE_INDEX can be over written by SPL MALLOC section.
> + */
> + store_boot_info_from_rom();
> +
> + /* Make all control module registers accessible */
> + ctrl_mmr_unlock();
> +
> + if (IS_ENABLED(CONFIG_CPU_V7R)) {
> + disable_linefill_optimization();
> + setup_k3_mpu_regions();
> + }
> +
> + /* Init DM early */
> + spl_early_init();
> +
> + /* Prepare console output */
> + preloader_console_init();
> +
> + if (IS_ENABLED(CONFIG_K3_LOAD_SYSFW)) {
> + /*
> + * Process pinctrl for the serial0 a.k.a. WKUP_UART0 module and continue
> + * regardless of the result of pinctrl. Do this without probing the
> + * device, but instead by searching the device that would request the
> + * given sequence number if probed. The UART will be used by the system
> + * firmware (SYSFW) image for various purposes and SYSFW depends on us
> + * to initialize its pin settings.
> + */
> + ret = uclass_find_device_by_seq(UCLASS_SERIAL, 0, &dev);
> + if (!ret)
> + pinctrl_select_state(dev, "default");
> +
> + /*
> + * Load, start up, and configure system controller firmware. Provide
> + * the U-Boot console init function to the SYSFW post-PM configuration
> + * callback hook, effectively switching on (or over) the console
> + * output.
> + */
> + k3_sysfw_loader(is_rom_loaded_sysfw(&bootdata),
> + k3_mmc_stop_clock, k3_mmc_restart_clock);
> +
> + if (IS_ENABLED(CONFIG_SPL_CLK_K3)) {
> + /*
> + * Force probe of clk_k3 driver here to ensure basic default clock
> + * configuration is always done for enabling PM services.
> + */
> + ret = uclass_get_device_by_driver(UCLASS_CLK,
> + DM_DRIVER_GET(ti_clk),
> + &dev);
> + if (ret)
> + panic("Failed to initialize clk-k3!\n");
> + }
> + }
> +
> + /* Output System Firmware version info */
> + k3_sysfw_print_ver();
> +
> + if (IS_ENABLED(CONFIG_TARGET_J721S2_R5_EVM)) {
> + ret = uclass_get_device_by_name(UCLASS_MISC, "msmc", &dev);
> + if (ret)
> + panic("Probe of msmc failed: %d\n", ret);
> +
> + ret = uclass_get_device(UCLASS_RAM, 0, &dev);
> + if (ret)
> + panic("DRAM 0 init failed: %d\n", ret);
> +
> + ret = uclass_next_device(&dev);
> + if (ret)
> + panic("DRAM 1 init failed: %d\n", ret);
> + }
> + spl_enable_dcache();
> +}
> +
> +u32 spl_mmc_boot_mode(const u32 boot_device)
> +{
> + switch (boot_device) {
> + case BOOT_DEVICE_MMC1:
> + return MMCSD_MODE_EMMCBOOT;
> + case BOOT_DEVICE_MMC2:
> + return MMCSD_MODE_FS;
> + default:
> + return MMCSD_MODE_RAW;
> + }
> +}
> +
> +static u32 __get_backup_bootmedia(u32 main_devstat)
> +{
> + u32 bkup_boot = (main_devstat & MAIN_DEVSTAT_BKUP_BOOTMODE_MASK) >>
> + MAIN_DEVSTAT_BKUP_BOOTMODE_SHIFT;
> +
> + switch (bkup_boot) {
> + case BACKUP_BOOT_DEVICE_USB:
> + return BOOT_DEVICE_DFU;
> + case BACKUP_BOOT_DEVICE_UART:
> + return BOOT_DEVICE_UART;
> + case BACKUP_BOOT_DEVICE_ETHERNET:
> + return BOOT_DEVICE_ETHERNET;
> + case BACKUP_BOOT_DEVICE_MMC2:
> + {
> + u32 port = (main_devstat & MAIN_DEVSTAT_BKUP_MMC_PORT_MASK) >>
> + MAIN_DEVSTAT_BKUP_MMC_PORT_SHIFT;
> + if (port == 0x0)
> + return BOOT_DEVICE_MMC1;
> + return BOOT_DEVICE_MMC2;
> + }
> + case BACKUP_BOOT_DEVICE_SPI:
> + return BOOT_DEVICE_SPI;
> + case BACKUP_BOOT_DEVICE_I2C:
> + return BOOT_DEVICE_I2C;
> + }
> +
> + return BOOT_DEVICE_RAM;
> +}
> +
> +static u32 __get_primary_bootmedia(u32 main_devstat, u32 wkup_devstat)
> +{
> + u32 bootmode = (wkup_devstat & WKUP_DEVSTAT_PRIMARY_BOOTMODE_MASK) >>
> + WKUP_DEVSTAT_PRIMARY_BOOTMODE_SHIFT;
> +
> + bootmode |= (main_devstat & MAIN_DEVSTAT_BOOT_MODE_B_MASK) <<
> + BOOT_MODE_B_SHIFT;
> +
> + if (bootmode == BOOT_DEVICE_OSPI || bootmode == BOOT_DEVICE_QSPI ||
> + bootmode == BOOT_DEVICE_XSPI)
> + bootmode = BOOT_DEVICE_SPI;
> +
> + if (bootmode == BOOT_DEVICE_MMC2) {
> + u32 port = (main_devstat &
> + MAIN_DEVSTAT_PRIM_BOOTMODE_MMC_PORT_MASK) >>
> + MAIN_DEVSTAT_PRIM_BOOTMODE_PORT_SHIFT;
> + if (port == 0x0)
> + bootmode = BOOT_DEVICE_MMC1;
> + }
> +
> + return bootmode;
> +}
> +
> +u32 spl_boot_device(void)
> +{
> + u32 wkup_devstat = readl(CTRLMMR_WKUP_DEVSTAT);
> + u32 main_devstat;
> +
> + if (wkup_devstat & WKUP_DEVSTAT_MCU_OMLY_MASK) {
> + printf("ERROR: MCU only boot is not yet supported\n");
> + return BOOT_DEVICE_RAM;
> + }
> +
> + /* MAIN CTRL MMR can only be read if MCU ONLY is 0 */
> + main_devstat = readl(CTRLMMR_MAIN_DEVSTAT);
> +
> + if (bootindex == K3_PRIMARY_BOOTMODE)
> + return __get_primary_bootmedia(main_devstat, wkup_devstat);
> + else
> + return __get_backup_bootmedia(main_devstat);
> +}
> +#endif
> +
> +#define J721S2_DEV_MCU_RTI0 295
> +#define J721S2_DEV_MCU_RTI1 296
> +#define J721S2_DEV_MCU_ARMSS0_CPU0 284
> +#define J721S2_DEV_MCU_ARMSS0_CPU1 285
> +
> +void release_resources_for_core_shutdown(void)
> +{
> + if (IS_ENABLED(CONFIG_SYS_K3_SPL_ATF)) {
> + struct ti_sci_handle *ti_sci;
> + struct ti_sci_dev_ops *dev_ops;
> + struct ti_sci_proc_ops *proc_ops;
> + int ret;
> + u32 i;
> +
> + const u32 put_device_ids[] = {
> + J721S2_DEV_MCU_RTI0,
> + J721S2_DEV_MCU_RTI1,
> + };
> +
> + ti_sci = get_ti_sci_handle();
> + dev_ops = &ti_sci->ops.dev_ops;
> + proc_ops = &ti_sci->ops.proc_ops;
> +
> + /* Iterate through list of devices to put (shutdown) */
> + for (i = 0; i < ARRAY_SIZE(put_device_ids); i++) {
> + u32 id = put_device_ids[i];
> +
> + ret = dev_ops->put_device(ti_sci, id);
> + if (ret)
> + panic("Failed to put device %u (%d)\n", id, ret);
> + }
> +
> + const u32 put_core_ids[] = {
> + J721S2_DEV_MCU_ARMSS0_CPU1,
> + J721S2_DEV_MCU_ARMSS0_CPU0, /* Handle CPU0 after CPU1 */
> + };
> +
> + /* Iterate through list of cores to put (shutdown) */
> + for (i = 0; i < ARRAY_SIZE(put_core_ids); i++) {
> + u32 id = put_core_ids[i];
> +
> + /*
> + * Queue up the core shutdown request. Note that this call
> + * needs to be followed up by an actual invocation of an WFE
> + * or WFI CPU instruction.
> + */
> + ret = proc_ops->proc_shutdown_no_wait(ti_sci, id);
> + if (ret)
> + panic("Failed sending core %u shutdown message (%d)\n",
> + id, ret);
> + }
> + }
> +}
> diff --git a/include/configs/j721s2_evm.h b/include/configs/j721s2_evm.h
> new file mode 100644
> index 000000000000..6fd098c957c3
> --- /dev/null
> +++ b/include/configs/j721s2_evm.h
> @@ -0,0 +1,191 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Configuration header file for K3 J721S2 EVM
> + *
> + * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
> + * David Huang <d-huang at ti.com>
> + */
> +
> +#ifndef __CONFIG_J721S2_EVM_H
> +#define __CONFIG_J721S2_EVM_H
> +
> +#include <linux/sizes.h>
> +#include <config_distro_bootcmd.h>
> +#include <environment/ti/mmc.h>
> +#include <environment/ti/k3_rproc.h>
> +#include <environment/ti/ufs.h>
> +#include <environment/ti/k3_dfu.h>
> +
> +/* DDR Configuration */
> +#define CONFIG_SYS_SDRAM_BASE1 0x880000000
> +
> +/* SPL Loader Configuration */
> +#if defined(CONFIG_TARGET_J721S2_A72_EVM) || defined(CONFIG_TARGET_J7200_A72_EVM)
> +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SPL_TEXT_BASE + \
> + CONFIG_SYS_K3_NON_SECURE_MSRAM_SIZE)
> +#define CONFIG_SYS_UBOOT_BASE 0x50280000
> +/* Image load address in RAM for DFU boot*/
> +#else
> +#define CONFIG_SYS_UBOOT_BASE 0x50080000
> +/*
> + * Maximum size in memory allocated to the SPL BSS. Keep it as tight as
> + * possible (to allow the build to go through), as this directly affects
> + * our memory footprint. The less we use for BSS the more we have available
> + * for everything else.
> + */
> +#define CONFIG_SPL_BSS_MAX_SIZE 0xA000
> +/*
> + * Link BSS to be within SPL in a dedicated region located near the top of
> + * the MCU SRAM, this way making it available also before relocation. Note
> + * that we are not using the actual top of the MCU SRAM as there is a memory
> + * location filled in by the boot ROM that we want to read out without any
> + * interference from the C context.
> + */
> +#define CONFIG_SPL_BSS_START_ADDR (0x41c80000 -\
> + CONFIG_SPL_BSS_MAX_SIZE)
> +/* Set the stack right below the SPL BSS section */
> +#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SPL_BSS_START_ADDR
> +/* Configure R5 SPL post-relocation malloc pool in DDR */
> +#define CONFIG_SYS_SPL_MALLOC_START 0x84000000
> +#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_16M
> +/* Image load address in RAM for DFU boot*/
> +#endif
> +
> +#ifdef CONFIG_SYS_K3_SPL_ATF
> +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "tispl.bin"
> +#endif
> +
> +#define CONFIG_SPL_MAX_SIZE CONFIG_SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE
> +
> +#define CONFIG_SYS_BOOTM_LEN SZ_64M
> +#define CONFIG_CQSPI_REF_CLK 133333333
> +
> +/* HyperFlash related configuration */
> +#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1
> +
> +/* U-Boot general configuration */
> +#define EXTRA_ENV_J721S2_BOARD_SETTINGS \
> + "default_device_tree=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
> + "findfdt=" \
> + "setenv name_fdt ${default_device_tree};" \
> + "setenv fdtfile ${name_fdt}\0" \
> + "name_kern=Image\0" \
> + "console=ttyS2,115200n8\0" \
> + "args_all=setenv optargs earlycon=ns16550a,mmio32,0x02880000 " \
> + "${mtdparts}\0" \
> + "run_kern=booti ${loadaddr} ${rd_spec} ${fdtaddr}\0"
> +
> +#define PARTS_DEFAULT \
> + /* Linux partitions */ \
> + "uuid_disk=${uuid_gpt_disk};" \
> + "name=rootfs,start=0,size=-,uuid=${uuid_gpt_rootfs}\0"
> +
> +#ifdef CONFIG_SYS_K3_SPL_ATF
> +#if defined(CONFIG_TARGET_J721S2_R5_EVM)
> +#define EXTRA_ENV_R5_SPL_RPROC_FW_ARGS_MMC \
> + "addr_mcur5f0_0load=0x89000000\0" \
> + "name_mcur5f0_0fw=/lib/firmware/j7-mcu-r5f0_0-fw\0"
> +#elif defined(CONFIG_TARGET_J7200_R5_EVM)
> +#define EXTRA_ENV_R5_SPL_RPROC_FW_ARGS_MMC \
> + "addr_mcur5f0_0load=0x89000000\0" \
> + "name_mcur5f0_0fw=/lib/firmware/j7200-mcu-r5f0_0-fw\0"
> +#endif /* CONFIG_TARGET_J721S2_R5_EVM */
> +#else
> +#define EXTRA_ENV_R5_SPL_RPROC_FW_ARGS_MMC ""
> +#endif /* CONFIG_SYS_K3_SPL_ATF */
> +
> +/* U-Boot MMC-specific configuration */
> +#define EXTRA_ENV_J721S2_BOARD_SETTINGS_MMC \
> + "boot=mmc\0" \
> + "mmcdev=1\0" \
> + "bootpart=1:2\0" \
> + "bootdir=/boot\0" \
> + EXTRA_ENV_R5_SPL_RPROC_FW_ARGS_MMC \
> + "rd_spec=-\0" \
> + "init_mmc=run args_all args_mmc\0" \
> + "get_fdt_mmc=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${name_fdt}\0" \
> + "get_overlay_mmc=" \
> + "fdt address ${fdtaddr};" \
> + "fdt resize 0x100000;" \
> + "for overlay in $name_overlays;" \
> + "do;" \
> + "load mmc ${bootpart} ${dtboaddr} ${bootdir}/${overlay} && " \
> + "fdt apply ${dtboaddr};" \
> + "done;\0" \
> + "partitions=" PARTS_DEFAULT \
> + "get_kern_mmc=load mmc ${bootpart} ${loadaddr} " \
> + "${bootdir}/${name_kern}\0" \
> + "get_fit_mmc=load mmc ${bootpart} ${addr_fit} " \
> + "${bootdir}/${name_fit}\0" \
> + "partitions=" PARTS_DEFAULT
> +
> +/* Set the default list of remote processors to boot */
> +#if defined(CONFIG_TARGET_J721S2_A72_EVM) || defined(CONFIG_TARGET_J7200_A72_EVM)
> +#ifdef DEFAULT_RPROCS
> +#undef DEFAULT_RPROCS
> +#endif
> +#endif
> +
> +#ifdef CONFIG_TARGET_J721S2_A72_EVM
> +#define DEFAULT_RPROCS "" \
> + "2 /lib/firmware/j721s2-main-r5f0_0-fw " \
> + "3 /lib/firmware/j721s2-main-r5f0_1-fw " \
> + "4 /lib/firmware/j721s2-main-r5f1_0-fw " \
> + "5 /lib/firmware/j721s2-main-r5f1_1-fw " \
> + "6 /lib/firmware/j721s2-c71_0-fw " \
> + "7 /lib/firmware/j721s2-c71_1-fw "
> +#endif /* CONFIG_TARGET_J721S2_A72_EVM */
> +
> +#ifdef CONFIG_TARGET_J7200_A72_EVM
> +#define EXTRA_ENV_CONFIG_MAIN_CPSW0_QSGMII_PHY \
> + "do_main_cpsw0_qsgmii_phyinit=1\0" \
> + "init_main_cpsw0_qsgmii_phy=gpio set gpio at 22_17;" \
> + "gpio clear gpio at 22_16\0" \
> + "main_cpsw0_qsgmii_phyinit=" \
> + "if test ${do_main_cpsw0_qsgmii_phyinit} -eq 1 && test ${dorprocboot} -eq 1 && " \
> + "test ${boot} = mmc; then " \
> + "run init_main_cpsw0_qsgmii_phy;" \
> + "fi;\0"
> +#define DEFAULT_RPROCS "" \
> + "2 /lib/firmware/j7200-main-r5f0_0-fw " \
> + "3 /lib/firmware/j7200-main-r5f0_1-fw "
> +#endif /* CONFIG_TARGET_J7200_A72_EVM */
> +
> +#ifndef EXTRA_ENV_CONFIG_MAIN_CPSW0_QSGMII_PHY
> +#define EXTRA_ENV_CONFIG_MAIN_CPSW0_QSGMII_PHY
> +#endif
> +
> +/* set default dfu_bufsiz to 128KB (sector size of OSPI) */
> +#define EXTRA_ENV_DFUARGS \
> + DFU_ALT_INFO_MMC \
> + DFU_ALT_INFO_EMMC \
> + DFU_ALT_INFO_RAM \
> + DFU_ALT_INFO_OSPI
> +
> +#if defined(CONFIG_TARGET_J721S2_A72_EVM) || defined(CONFIG_TARGET_J7200_A72_EVM)
> +#define EXTRA_ENV_J721S2_BOARD_SETTINGS_MTD \
> + "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
> + "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0"
> +#else
> +#define EXTRA_ENV_J721S2_BOARD_SETTINGS_MTD
> +#endif
> +
> +/* Incorporate settings into the U-Boot environment */
> +#define CONFIG_EXTRA_ENV_SETTINGS \
> + DEFAULT_LINUX_BOOT_ENV \
> + DEFAULT_MMC_TI_ARGS \
> + DEFAULT_FIT_TI_ARGS \
> + EXTRA_ENV_J721S2_BOARD_SETTINGS \
> + EXTRA_ENV_J721S2_BOARD_SETTINGS_MMC \
> + EXTRA_ENV_RPROC_SETTINGS \
> + EXTRA_ENV_DFUARGS \
> + DEFAULT_UFS_TI_ARGS \
> + EXTRA_ENV_J721S2_BOARD_SETTINGS_MTD \
> + EXTRA_ENV_CONFIG_MAIN_CPSW0_QSGMII_PHY
> +
> +/* Now for the remaining common defines */
> +#include <configs/ti_armv7_common.h>
> +
> +/* MMC ENV related defines */
> +
> +#endif /* __CONFIG_J721S2_EVM_H */
>
More information about the U-Boot
mailing list