[PATCH] pci: pci_mvebu: Add support for Kirkwood PCIe controllers

[Stefan Roese]

On 1/13/22 14:28, Pali Rohár wrote:
> Kirkwood uses macros KW_DEFADR_PCI_MEM and KW_DEFADR_PCI_IO for base
> address of PCIe mappings. Size of PCIe windows is not defined in any macro
> yet, so export them in new KW_DEFADR_PCI_MEM_SIZE and KW_DEFADR_PCI_IO_SIZE
> macros.
> 
> Kirkwood arch code already maps mbus windows for io and mem, so avoid
> calling mvebu_mbus_add_window_by_id() function which would try to do
> duplicate window mapping.
> 
> Kirkwood PCIe controllers already use "marvell,kirkwood-pcie" DT compatible
> string, so mark pci_mvebu.c driver as compatible for it.
> 
> Signed-off-by: Pali Rohár <pali at kernel.org>

Applied to u-boot-marvell/master

Thanks,
Stefan

> ---
> This patch depends on series "mvebu: Move PCIe code from serdes to PCIe driver":
> https://patchwork.ozlabs.org/project/uboot/list/?series=277906&state=*
> 
> Tony, could you please test it in Kirwood hardware?
> ---
>   arch/arm/mach-kirkwood/cpu.c              |  4 ++--
>   arch/arm/mach-kirkwood/include/mach/cpu.h |  3 +++
>   drivers/pci/Kconfig                       |  6 +++---
>   drivers/pci/pci_mvebu.c                   | 16 ++++++++++++++++
>   4 files changed, 24 insertions(+), 5 deletions(-)
> 
> diff --git a/arch/arm/mach-kirkwood/cpu.c b/arch/arm/mach-kirkwood/cpu.c
> index e9571298a824..80f893ab369a 100644
> --- a/arch/arm/mach-kirkwood/cpu.c
> +++ b/arch/arm/mach-kirkwood/cpu.c
> @@ -54,11 +54,11 @@ unsigned int kw_winctrl_calcsize(unsigned int sizeval)
>   
>   static struct mbus_win windows[] = {
>   	/* Window 0: PCIE MEM address space */
> -	{ KW_DEFADR_PCI_MEM, 1024 * 1024 * 256,
> +	{ KW_DEFADR_PCI_MEM, KW_DEFADR_PCI_MEM_SIZE,
>   	  KWCPU_TARGET_PCIE, KWCPU_ATTR_PCIE_MEM },
>   
>   	/* Window 1: PCIE IO address space */
> -	{ KW_DEFADR_PCI_IO, 1024 * 64,
> +	{ KW_DEFADR_PCI_IO, KW_DEFADR_PCI_IO_SIZE,
>   	  KWCPU_TARGET_PCIE, KWCPU_ATTR_PCIE_IO },
>   
>   	/* Window 2: NAND Flash address space */
> diff --git a/arch/arm/mach-kirkwood/include/mach/cpu.h b/arch/arm/mach-kirkwood/include/mach/cpu.h
> index ea42182cf9c6..71c546f9acf6 100644
> --- a/arch/arm/mach-kirkwood/include/mach/cpu.h
> +++ b/arch/arm/mach-kirkwood/include/mach/cpu.h
> @@ -68,6 +68,9 @@ enum kwcpu_attrib {
>   #define KW_DEFADR_SPIF		0xE8000000
>   #define KW_DEFADR_BOOTROM	0xF8000000
>   
> +#define KW_DEFADR_PCI_MEM_SIZE	(1024 * 1024 * 256)
> +#define KW_DEFADR_PCI_IO_SIZE	(1024 * 64)
> +
>   struct mbus_win {
>   	u32 base;
>   	u32 size;
> diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
> index 630d6e6cc5ee..69141344c869 100644
> --- a/drivers/pci/Kconfig
> +++ b/drivers/pci/Kconfig
> @@ -262,13 +262,13 @@ config PCIE_IPROC
>   	  Say Y here if you want to enable Broadcom iProc PCIe controller,
>   
>   config PCI_MVEBU
> -	bool "Enable Armada XP/38x PCIe driver"
> -	depends on ARCH_MVEBU
> +	bool "Enable Kirkwood / Armada 370/XP/375/38x PCIe driver"
> +	depends on (ARCH_KIRKWOOD || ARCH_MVEBU)
>   	select MISC
>   	select DM_RESET
>   	help
>   	  Say Y here if you want to enable PCIe controller support on
> -	  Armada XP/38x SoCs.
> +	  Kirkwood and Armada 370/XP/375/38x SoCs.
>   
>   config PCIE_DW_COMMON
>   	bool
> diff --git a/drivers/pci/pci_mvebu.c b/drivers/pci/pci_mvebu.c
> index b3ea034a2847..d99a99bae940 100644
> --- a/drivers/pci/pci_mvebu.c
> +++ b/drivers/pci/pci_mvebu.c
> @@ -498,6 +498,13 @@ static int mvebu_pcie_probe(struct udevice *dev)
>   	mvebu_pcie_set_local_bus_nr(pcie, 0);
>   	mvebu_pcie_set_local_dev_nr(pcie, 1);
>   
> +	/*
> +	 * Kirkwood arch code already maps mbus windows for PCIe IO and MEM.
> +	 * So skip calling mvebu_mbus_add_window_by_id() function as it would
> +	 * fail on error "conflicts with another window" which means conflict
> +	 * with existing PCIe window mappings.
> +	 */
> +#ifndef CONFIG_ARCH_KIRKWOOD
>   	if (resource_size(&pcie->mem) &&
>   	    mvebu_mbus_add_window_by_id(pcie->mem_target, pcie->mem_attr,
>   					(phys_addr_t)pcie->mem.start,
> @@ -519,6 +526,7 @@ static int mvebu_pcie_probe(struct udevice *dev)
>   		pcie->io.start = 0;
>   		pcie->io.end = -1;
>   	}
> +#endif
>   
>   	/* Setup windows and configure host bridge */
>   	mvebu_pcie_setup_wins(pcie);
> @@ -725,10 +733,17 @@ static int mvebu_pcie_bind(struct udevice *parent)
>   	}
>   	ports_count = 0;
>   
> +#ifdef CONFIG_ARCH_KIRKWOOD
> +	mem.start = KW_DEFADR_PCI_MEM;
> +	mem.end = KW_DEFADR_PCI_MEM + KW_DEFADR_PCI_MEM_SIZE - 1;
> +	io.start = KW_DEFADR_PCI_IO;
> +	io.end = KW_DEFADR_PCI_IO + KW_DEFADR_PCI_IO_SIZE - 1;
> +#else
>   	mem.start = MBUS_PCI_MEM_BASE;
>   	mem.end = MBUS_PCI_MEM_BASE + MBUS_PCI_MEM_SIZE - 1;
>   	io.start = MBUS_PCI_IO_BASE;
>   	io.end = MBUS_PCI_IO_BASE + MBUS_PCI_IO_SIZE - 1;
> +#endif
>   
>   	/* First phase: Fill mvebu_pcie struct for each port */
>   	ofnode_for_each_subnode(subnode, dev_ofnode(parent)) {
> @@ -809,6 +824,7 @@ static int mvebu_pcie_bind(struct udevice *parent)
>   static const struct udevice_id mvebu_pcie_ids[] = {
>   	{ .compatible = "marvell,armada-xp-pcie" },
>   	{ .compatible = "marvell,armada-370-pcie" },
> +	{ .compatible = "marvell,kirkwood-pcie" },
>   	{ }
>   };
>   
> 

Viele Grüße,
Stefan Roese

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