[PATCH 10/11] ARM: dts: suniv: Add device tree files for F1C100s
Jesse Taube
mr.bossman075 at gmail.com
Fri Jan 21 03:12:46 CET 2022
On 1/20/22 20:59, Andre Przywara wrote:
> On Tue, 4 Jan 2022 19:35:07 -0500
> Jesse Taube <mr.bossman075 at gmail.com> wrote:
>
> Hi,
>
>> From: Icenowy Zheng <icenowy at aosc.io>
>>
>> Add device tree files for suniv and
>> Lichee Pi Nano it is a board based on F1C100s.
>>
>> Signed-off-by: Icenowy Zheng <icenowy at aosc.io>
>> Signed-off-by: Jesse Taube <Mr.Bossman075 at gmail.com>
>
> Those files differ significantly from the kernel. It looks like the
> copies here enable MMC, SPI and USB, which are missing from the Linux
> tree.
Thx for pointing this out I will fix it. Although SPI and MMC are the
two boot devices so they will be needed. I'm confused as to why and how
they arent' in Linux as they have drivers, USB even has a driver.
Thanks for the Reviews!
Kindly,
Jesse Taube
At the same time both seem to be coming from a slightly different
> base. So I'd suggest to fix this up (create a minimal diff between
> Linux and this, changing this version if needed), then sending this to
> the kernel. Meanwhile we could go with the mainline Linux versions. I
> am willing to merge them once the updates reach some maintainer tree.
>
> Cheers,
> Andre
>
>> ---
>> arch/arm/dts/Makefile | 2 +
>> arch/arm/dts/suniv-f1c100s-licheepi-nano.dts | 64 ++++++
>> arch/arm/dts/suniv-f1c100s.dtsi | 6 +
>> arch/arm/dts/suniv.dtsi | 224 +++++++++++++++++++
>> 4 files changed, 296 insertions(+)
>> create mode 100644 arch/arm/dts/suniv-f1c100s-licheepi-nano.dts
>> create mode 100644 arch/arm/dts/suniv-f1c100s.dtsi
>> create mode 100644 arch/arm/dts/suniv.dtsi
>>
>> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
>> index 453e2fd1a9..07030deeca 100644
>> --- a/arch/arm/dts/Makefile
>> +++ b/arch/arm/dts/Makefile
>> @@ -497,6 +497,8 @@ dtb-$(CONFIG_STM32H7) += stm32h743i-disco.dtb \
>> stm32h743i-eval.dtb \
>> stm32h750i-art-pi.dtb
>>
>> +dtb-$(CONFIG_MACH_SUNIV) += \
>> + suniv-f1c100s-licheepi-nano.dtb
>> dtb-$(CONFIG_MACH_SUN4I) += \
>> sun4i-a10-a1000.dtb \
>> sun4i-a10-ba10-tvbox.dtb \
>> diff --git a/arch/arm/dts/suniv-f1c100s-licheepi-nano.dts b/arch/arm/dts/suniv-f1c100s-licheepi-nano.dts
>> new file mode 100644
>> index 0000000000..919fc01b0e
>> --- /dev/null
>> +++ b/arch/arm/dts/suniv-f1c100s-licheepi-nano.dts
>> @@ -0,0 +1,64 @@
>> +// SPDX-License-Identifier: (GPL-2.0+ OR X11)
>> +/*
>> + * Copyright 2018 Icenowy Zheng <icenowy at aosc.io>
>> + */
>> +
>> +/dts-v1/;
>> +#include "suniv-f1c100s.dtsi"
>> +
>> +#include <dt-bindings/gpio/gpio.h>
>> +
>> +/ {
>> + model = "Lichee Pi Nano";
>> + compatible = "licheepi,licheepi-nano", "allwinner,suniv-f1c100s",
>> + "allwinner,suniv";
>> +
>> + aliases {
>> + serial0 = &uart0;
>> + spi0 = &spi0;
>> + };
>> +
>> + chosen {
>> + stdout-path = "serial0:115200n8";
>> + };
>> +};
>> +
>> +&otg_sram {
>> + status = "okay";
>> +};
>> +
>> +&mmc0 {
>> + bus-width = <4>;
>> + cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
>> + status = "okay";
>> +};
>> +
>> +&spi0 {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&spi0_pins_a>;
>> + status = "okay";
>> +
>> + flash at 0 {
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + compatible = "winbond,w25q128", "jedec,spi-nor";
>> + reg = <0>;
>> + spi-max-frequency = <40000000>;
>> + };
>> +};
>> +
>> +&uart0 {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&uart0_pins_a>;
>> + status = "okay";
>> +};
>> +
>> +&usb_otg {
>> + dr_mode = "otg";
>> + status = "okay";
>> +};
>> +
>> +&usbphy {
>> + usb0_id_det-gpio = <&pio 4 2 GPIO_ACTIVE_HIGH>; /* PE2 */
>> + status = "okay";
>> +};
>> diff --git a/arch/arm/dts/suniv-f1c100s.dtsi b/arch/arm/dts/suniv-f1c100s.dtsi
>> new file mode 100644
>> index 0000000000..f084bc8dd1
>> --- /dev/null
>> +++ b/arch/arm/dts/suniv-f1c100s.dtsi
>> @@ -0,0 +1,6 @@
>> +// SPDX-License-Identifier: (GPL-2.0+ OR X11)
>> +/*
>> + * Copyright 2018 Icenowy Zheng <icenowy at aosc.io>
>> + */
>> +
>> +#include "suniv.dtsi"
>> diff --git a/arch/arm/dts/suniv.dtsi b/arch/arm/dts/suniv.dtsi
>> new file mode 100644
>> index 0000000000..a4e933505d
>> --- /dev/null
>> +++ b/arch/arm/dts/suniv.dtsi
>> @@ -0,0 +1,224 @@
>> +// SPDX-License-Identifier: (GPL-2.0+ OR X11)
>> +/*
>> + * Copyright 2018 Icenowy Zheng <icenowy at aosc.io>
>> + */
>> +
>> +#include <dt-bindings/clock/suniv-ccu.h>
>> +#include <dt-bindings/reset/suniv-ccu.h>
>> +
>> +/ {
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + interrupt-parent = <&intc>;
>> +
>> + clocks {
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + ranges;
>> +
>> + osc24M: clk-24M {
>> + #clock-cells = <0>;
>> + compatible = "fixed-clock";
>> + clock-frequency = <24000000>;
>> + clock-output-names = "osc24M";
>> + };
>> +
>> + osc32k: clk-32k {
>> + #clock-cells = <0>;
>> + compatible = "fixed-clock";
>> + clock-frequency = <32768>;
>> + clock-output-names = "osc32k";
>> + };
>> +
>> + fake100M: clk-100M {
>> + #clock-cells = <0>;
>> + compatible = "fixed-clock";
>> + clock-frequency = <100000000>;
>> + clock-output-names = "fake-100M";
>> + };
>> + };
>> +
>> + cpus {
>> + #address-cells = <0>;
>> + #size-cells = <0>;
>> +
>> + cpu {
>> + compatible = "arm,arm926ej-s";
>> + device_type = "cpu";
>> + };
>> + };
>> +
>> + soc {
>> + compatible = "simple-bus";
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + ranges;
>> +
>> + sram-controller at 1c00000 {
>> + compatible = "allwinner,sun4i-a10-sram-controller";
>> + reg = <0x01c00000 0x30>;
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + ranges;
>> +
>> + sram_d: sram at 10000 {
>> + compatible = "mmio-sram";
>> + reg = <0x00010000 0x1000>;
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + ranges = <0 0x00010000 0x1000>;
>> +
>> + otg_sram: sram-section at 0 {
>> + compatible = "allwinner,sun4i-a10-sram-d";
>> + reg = <0x0000 0x1000>;
>> + status = "disabled";
>> + };
>> + };
>> + };
>> +
>> + spi0: spi at 1c05000 {
>> + compatible = "allwinner,suniv-spi",
>> + "allwinner,sun8i-h3-spi";
>> + reg = <0x01c05000 0x1000>;
>> + interrupts = <10>;
>> + clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_BUS_SPI0>;
>> + clock-names = "ahb", "mod";
>> + resets = <&ccu RST_BUS_SPI0>;
>> + status = "disabled";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + };
>> +
>> + mmc0: mmc at 1c0f000 {
>> + compatible = "allwinner,sun4i-a10-mmc";
>> + reg = <0x01c0f000 0x1000>;
>> + clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
>> + clock-names = "ahb", "mmc";
>> + interrupts = <32>;
>> + resets = <&ccu RST_BUS_MMC0>;
>> + reset-names = "ahb";
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&mmc0_pins>;
>> + status = "disabled";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + };
>> +
>> + ccu: clock at 1c20000 {
>> + compatible = "allwinner,suniv-ccu";
>> + reg = <0x01c20000 0x400>;
>> + clocks = <&osc24M>, <&osc32k>;
>> + clock-names = "hosc", "losc";
>> + #clock-cells = <1>;
>> + #reset-cells = <1>;
>> + };
>> +
>> + intc: interrupt-controller at 1c20400 {
>> + compatible = "allwinner,suniv-ic";
>> + reg = <0x01c20400 0x400>;
>> + interrupt-controller;
>> + #interrupt-cells = <1>;
>> + };
>> +
>> + pio: pinctrl at 1c20800 {
>> + compatible = "allwinner,suniv-pinctrl";
>> + reg = <0x01c20800 0x400>;
>> + interrupts = <38>, <39>, <40>;
>> + clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>;
>> + clock-names = "apb", "hosc", "losc";
>> + gpio-controller;
>> + interrupt-controller;
>> + #interrupt-cells = <3>;
>> + #gpio-cells = <3>;
>> +
>> + spi0_pins_a: spi0-pins-pc {
>> + pins = "PC0", "PC1", "PC2", "PC3";
>> + function = "spi0";
>> + };
>> +
>> + uart0_pins_a: uart-pins-pe {
>> + pins = "PE0", "PE1";
>> + function = "uart0";
>> + };
>> +
>> + mmc0_pins: mmc0-pins {
>> + pins = "PF0", "PF1", "PF2",
>> + "PF3", "PF4", "PF5";
>> + function = "mmc0";
>> + drive-strength = <30>;
>> + bias-pull-up;
>> + };
>> + };
>> +
>> + timer at 1c20c00 {
>> + compatible = "allwinner,sun4i-a10-timer";
>> + reg = <0x01c20c00 0x90>;
>> + interrupts = <13>;
>> + clocks = <&osc24M>;
>> + };
>> +
>> + wdt: watchdog at 1c20ca0 {
>> + compatible = "allwinner,sun6i-a31-wdt";
>> + reg = <0x01c20ca0 0x20>;
>> + };
>> +
>> + uart0: serial at 1c25000 {
>> + compatible = "snps,dw-apb-uart";
>> + reg = <0x01c25000 0x400>;
>> + interrupts = <1>;
>> + reg-shift = <2>;
>> + reg-io-width = <4>;
>> + clocks = <&ccu CLK_BUS_UART0>;
>> + resets = <&ccu RST_BUS_UART0>;
>> + status = "disabled";
>> + };
>> +
>> + uart1: serial at 1c25400 {
>> + compatible = "snps,dw-apb-uart";
>> + reg = <0x01c25400 0x400>;
>> + interrupts = <2>;
>> + reg-shift = <2>;
>> + reg-io-width = <4>;
>> + clocks = <&ccu CLK_BUS_UART1>;
>> + resets = <&ccu RST_BUS_UART1>;
>> + status = "disabled";
>> + };
>> +
>> + uart2: serial at 1c25800 {
>> + compatible = "snps,dw-apb-uart";
>> + reg = <0x01c25800 0x400>;
>> + interrupts = <3>;
>> + reg-shift = <2>;
>> + reg-io-width = <4>;
>> + clocks = <&ccu CLK_BUS_UART2>;
>> + resets = <&ccu RST_BUS_UART2>;
>> + status = "disabled";
>> + };
>> +
>> + usb_otg: usb at 1c13000 {
>> + compatible = "allwinner,suniv-musb";
>> + reg = <0x01c13000 0x0400>;
>> + clocks = <&ccu CLK_BUS_OTG>;
>> + resets = <&ccu RST_BUS_OTG>;
>> + interrupts = <26>;
>> + interrupt-names = "mc";
>> + phys = <&usbphy 0>;
>> + phy-names = "usb";
>> + extcon = <&usbphy 0>;
>> + allwinner,sram = <&otg_sram 1>;
>> + status = "disabled";
>> + };
>> +
>> + usbphy: phy at 1c13400 {
>> + compatible = "allwinner,suniv-usb-phy";
>> + reg = <0x01c13400 0x10>;
>> + reg-names = "phy_ctrl";
>> + clocks = <&ccu CLK_USB_PHY0>;
>> + clock-names = "usb0_phy";
>> + resets = <&ccu RST_USB_PHY0>;
>> + reset-names = "usb0_reset";
>> + #phy-cells = <1>;
>> + status = "disabled";
>> + };
>> + };
>> +};
>
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