[PATCH 1/3] serial: Add RISC-V HTIF console driver

Anup Patel apatel at ventanamicro.com
Tue Jan 25 12:31:43 CET 2022


On Tue, Jan 25, 2022 at 2:46 PM Bin Meng <bmeng.cn at gmail.com> wrote:
>
> On Tue, Jan 25, 2022 at 2:00 PM Anup Patel <apatel at ventanamicro.com> wrote:
> >
> > On Tue, Jan 25, 2022 at 10:22 AM Bin Meng <bmeng.cn at gmail.com> wrote:
> > >
> > > On Sat, Jan 15, 2022 at 12:20 AM Anup Patel <apatel at ventanamicro.com> wrote:
> > > >
> > > > Quite a few RISC-V emulators and ISS (including Spike) have host
> > > > transfer interface (HTIF) based console. This patch adds HTIF
> > > > based console driver for RISC-V platforms which depends totally
> > > > on DT node for HTIF register base address.
> > > >
> > > > Signed-off-by: Anup Patel <apatel at ventanamicro.com>
> > > > Reviewed-by: Philipp Tomsich <philipp.tomsich at vrull.eu>
> > > > ---
> > > >  drivers/serial/Kconfig       |   8 ++
> > > >  drivers/serial/Makefile      |   1 +
> > > >  drivers/serial/serial_htif.c | 178 +++++++++++++++++++++++++++++++++++
> > > >  3 files changed, 187 insertions(+)
> > > >  create mode 100644 drivers/serial/serial_htif.c
> > > >
> > > > diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
> > > > index 6c8fdda9a0..345d1881f5 100644
> > > > --- a/drivers/serial/Kconfig
> > > > +++ b/drivers/serial/Kconfig
> > > > @@ -866,6 +866,14 @@ config PXA_SERIAL
> > > >           If you have a machine based on a Marvell XScale PXA2xx CPU you
> > > >           can enable its onboard serial ports by enabling this option.
> > > >
> > > > +config HTIF_CONSOLE
> > > > +       bool "RISC-V HTIF console support"
> > > > +       depends on DM_SERIAL && 64BIT
> > >
> > > Does this driver not work on 32-bit?
> >
> > Only putc() works but getc() does not work on 32-bit. Same issue
> > is there with OpenSBI and BBL as well. That's why I have restricted
> > this driver to 64-bit only.
> >
>
> I don't get it. Is this a QEMU riscv32 bug?

It's a bug in the HTIF device itself. There is no documentation of
HTIF as well. All implementations (including QEMU spike) simply
follow how Spike ISS implements HTIF.

In other words, HTIF is yet another undocumented device in
RISC-V world.

Regards,
Anup


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