[PATCH v2 11/12] ARM: dts: suniv: Add device tree files for F1C100s
Andre Przywara
andre.przywara at arm.com
Sat Jan 29 03:37:20 CET 2022
On Fri, 28 Jan 2022 21:31:28 -0500
Jesse Taube <mr.bossman075 at gmail.com> wrote:
> On 1/28/22 21:25, Andre Przywara wrote:
> > On Wed, 26 Jan 2022 08:53:28 -0500
> > Jesse Taube <mr.bossman075 at gmail.com> wrote:
> >
> >> From: Icenowy Zheng <icenowy at aosc.io>
> >>
> >> Add device tree files for suniv and
> >> Lichee Pi Nano it is a board based on F1C100s.
> >
> > As mentioned in the other email, please do a 1:1 copy from the current
> > Linux tree. Yes, this will miss MMC and USB, but I am happy to take a
> > fixup patch on short notice when the respective kernel patches hit some
> > maintainer tree. > Cheers,
> Uh dts wont compile without a mmc node its a bug in another sunxi dts.
Not sure I follow, it compiles fine in the kernel, doesn't it?
> Also Icenowy's email chnaged to to .io not .xyz can i change that in this?
Please no changes compared to Linux, there is no "U-Boot DT", it's
the same hardware, so the same DT, just synced from the definitive
repository (the Linux tree).
Yes, the file split is different here, but that doesn't matter, just
copy the current Linux files.
Cheers,
Andre
> > Andre
> >
> >>
> >> Signed-off-by: Icenowy Zheng <icenowy at aosc.io>
> >> Signed-off-by: Jesse Taube <Mr.Bossman075 at gmail.com>
> >> ---
> >> V1->V2:
> >> * Sync with Linux
> >> * Re-add MMC node
> >> ---
> >> arch/arm/dts/Makefile | 2 +
> >> arch/arm/dts/suniv-f1c100s-licheepi-nano.dts | 29 ++++
> >> arch/arm/dts/suniv-f1c100s.dtsi | 6 +
> >> arch/arm/dts/suniv.dtsi | 160 +++++++++++++++++++
> >> 4 files changed, 197 insertions(+)
> >> create mode 100644 arch/arm/dts/suniv-f1c100s-licheepi-nano.dts
> >> create mode 100644 arch/arm/dts/suniv-f1c100s.dtsi
> >> create mode 100644 arch/arm/dts/suniv.dtsi
> >>
> >> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> >> index 453e2fd1a9..07030deeca 100644
> >> --- a/arch/arm/dts/Makefile
> >> +++ b/arch/arm/dts/Makefile
> >> @@ -497,6 +497,8 @@ dtb-$(CONFIG_STM32H7) += stm32h743i-disco.dtb \
> >> stm32h743i-eval.dtb \
> >> stm32h750i-art-pi.dtb
> >>
> >> +dtb-$(CONFIG_MACH_SUNIV) += \
> >> + suniv-f1c100s-licheepi-nano.dtb
> >> dtb-$(CONFIG_MACH_SUN4I) += \
> >> sun4i-a10-a1000.dtb \
> >> sun4i-a10-ba10-tvbox.dtb \
> >> diff --git a/arch/arm/dts/suniv-f1c100s-licheepi-nano.dts b/arch/arm/dts/suniv-f1c100s-licheepi-nano.dts
> >> new file mode 100644
> >> index 0000000000..9e89eec5bd
> >> --- /dev/null
> >> +++ b/arch/arm/dts/suniv-f1c100s-licheepi-nano.dts
> >> @@ -0,0 +1,29 @@
> >> +// SPDX-License-Identifier: (GPL-2.0+ OR X11)
> >> +/*
> >> + * Copyright 2018 Icenowy Zheng <icenowy at aosc.io>
> >> + */
> >> +
> >> +/dts-v1/;
> >> +#include "suniv-f1c100s.dtsi"
> >> +
> >> +#include <dt-bindings/gpio/gpio.h>
> >> +
> >> +/ {
> >> + model = "Lichee Pi Nano";
> >> + compatible = "licheepi,licheepi-nano", "allwinner,suniv-f1c100s",
> >> + "allwinner,suniv";
> >> +
> >> + aliases {
> >> + serial0 = &uart0;
> >> + };
> >> +
> >> + chosen {
> >> + stdout-path = "serial0:115200n8";
> >> + };
> >> +};
> >> +
> >> +&uart0 {
> >> + pinctrl-names = "default";
> >> + pinctrl-0 = <&uart0_pe_pins>;
> >> + status = "okay";
> >> +};
> >> diff --git a/arch/arm/dts/suniv-f1c100s.dtsi b/arch/arm/dts/suniv-f1c100s.dtsi
> >> new file mode 100644
> >> index 0000000000..f084bc8dd1
> >> --- /dev/null
> >> +++ b/arch/arm/dts/suniv-f1c100s.dtsi
> >> @@ -0,0 +1,6 @@
> >> +// SPDX-License-Identifier: (GPL-2.0+ OR X11)
> >> +/*
> >> + * Copyright 2018 Icenowy Zheng <icenowy at aosc.io>
> >> + */
> >> +
> >> +#include "suniv.dtsi"
> >> diff --git a/arch/arm/dts/suniv.dtsi b/arch/arm/dts/suniv.dtsi
> >> new file mode 100644
> >> index 0000000000..ad2bbb7a12
> >> --- /dev/null
> >> +++ b/arch/arm/dts/suniv.dtsi
> >> @@ -0,0 +1,160 @@
> >> +// SPDX-License-Identifier: (GPL-2.0+ OR X11)
> >> +/*
> >> + * Copyright 2018 Icenowy Zheng <icenowy at aosc.io>
> >> + */
> >> +
> >> +#include <dt-bindings/clock/suniv-ccu.h>
> >> +#include <dt-bindings/reset/suniv-ccu.h>
> >> +
> >> +/ {
> >> + #address-cells = <1>;
> >> + #size-cells = <1>;
> >> + interrupt-parent = <&intc>;
> >> +
> >> + clocks {
> >> + osc24M: clk-24M {
> >> + #clock-cells = <0>;
> >> + compatible = "fixed-clock";
> >> + clock-frequency = <24000000>;
> >> + clock-output-names = "osc24M";
> >> + };
> >> +
> >> + osc32k: clk-32k {
> >> + #clock-cells = <0>;
> >> + compatible = "fixed-clock";
> >> + clock-frequency = <32768>;
> >> + clock-output-names = "osc32k";
> >> + };
> >> + };
> >> +
> >> + cpus {
> >> + cpu {
> >> + compatible = "arm,arm926ej-s";
> >> + device_type = "cpu";
> >> + };
> >> + };
> >> +
> >> + soc {
> >> + compatible = "simple-bus";
> >> + #address-cells = <1>;
> >> + #size-cells = <1>;
> >> + ranges;
> >> +
> >> + sram-controller at 1c00000 {
> >> + compatible = "allwinner,suniv-f1c100s-system-control",
> >> + "allwinner,sun4i-a10-sram-controller";
> >> + reg = <0x01c00000 0x30>;
> >> + #address-cells = <1>;
> >> + #size-cells = <1>;
> >> + ranges;
> >> +
> >> + sram_d: sram at 10000 {
> >> + compatible = "mmio-sram";
> >> + reg = <0x00010000 0x1000>;
> >> + #address-cells = <1>;
> >> + #size-cells = <1>;
> >> + ranges = <0 0x00010000 0x1000>;
> >> +
> >> + otg_sram: sram-section at 0 {
> >> + compatible = "allwinner,suniv-f1c100s-sram-d",
> >> + "allwinner,sun4i-a10-sram-d";
> >> + reg = <0x0000 0x1000>;
> >> + status = "disabled";
> >> + };
> >> + };
> >> + };
> >> +
> >> + mmc0: mmc at 1c0f000 {
> >> + compatible = "allwinner,sun4i-a10-mmc";
> >> + reg = <0x01c0f000 0x1000>;
> >> + clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
> >> + clock-names = "ahb", "mmc";
> >> + interrupts = <32>;
> >> + resets = <&ccu RST_BUS_MMC0>;
> >> + reset-names = "ahb";
> >> + status = "disabled";
> >> + #address-cells = <1>;
> >> + #size-cells = <0>;
> >> + };
> >> +
> >> + ccu: clock at 1c20000 {
> >> + compatible = "allwinner,suniv-ccu";
> >> + reg = <0x01c20000 0x400>;
> >> + clocks = <&osc24M>, <&osc32k>;
> >> + clock-names = "hosc", "losc";
> >> + #clock-cells = <1>;
> >> + #reset-cells = <1>;
> >> + };
> >> +
> >> + intc: interrupt-controller at 1c20400 {
> >> + compatible = "allwinner,suniv-ic";
> >> + reg = <0x01c20400 0x400>;
> >> + interrupt-controller;
> >> + #interrupt-cells = <1>;
> >> + };
> >> +
> >> + pio: pinctrl at 1c20800 {
> >> + compatible = "allwinner,suniv-pinctrl";
> >> + reg = <0x01c20800 0x400>;
> >> + interrupts = <38>, <39>, <40>;
> >> + clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>;
> >> + clock-names = "apb", "hosc", "losc";
> >> + gpio-controller;
> >> + interrupt-controller;
> >> + #interrupt-cells = <3>;
> >> + #gpio-cells = <3>;
> >> +
> >> + uart0_pe_pins: uart0-pe-pins {
> >> + pins = "PE0", "PE1";
> >> + function = "uart0";
> >> + };
> >> + };
> >> +
> >> + timer at 1c20c00 {
> >> + compatible = "allwinner,suniv-f1c100s-timer",
> >> + "allwinner,sun4i-a10-timer";
> >> + reg = <0x01c20c00 0x90>;
> >> + interrupts = <13>;
> >> + clocks = <&osc24M>;
> >> + };
> >> +
> >> + wdt: watchdog at 1c20ca0 {
> >> + compatible = "allwinner,suniv-f1c100s-wdt",
> >> + "allwinner,sun6i-a31-wdt";
> >> + reg = <0x01c20ca0 0x20>;
> >> + };
> >> +
> >> + uart0: serial at 1c25000 {
> >> + compatible = "snps,dw-apb-uart";
> >> + reg = <0x01c25000 0x400>;
> >> + interrupts = <1>;
> >> + reg-shift = <2>;
> >> + reg-io-width = <4>;
> >> + clocks = <&ccu CLK_BUS_UART0>;
> >> + resets = <&ccu RST_BUS_UART0>;
> >> + status = "disabled";
> >> + };
> >> +
> >> + uart1: serial at 1c25400 {
> >> + compatible = "snps,dw-apb-uart";
> >> + reg = <0x01c25400 0x400>;
> >> + interrupts = <2>;
> >> + reg-shift = <2>;
> >> + reg-io-width = <4>;
> >> + clocks = <&ccu CLK_BUS_UART1>;
> >> + resets = <&ccu RST_BUS_UART1>;
> >> + status = "disabled";
> >> + };
> >> +
> >> + uart2: serial at 1c25800 {
> >> + compatible = "snps,dw-apb-uart";
> >> + reg = <0x01c25800 0x400>;
> >> + interrupts = <3>;
> >> + reg-shift = <2>;
> >> + reg-io-width = <4>;
> >> + clocks = <&ccu CLK_BUS_UART2>;
> >> + resets = <&ccu RST_BUS_UART2>;
> >> + status = "disabled";
> >> + };
> >> + };
> >> +};
> >
More information about the U-Boot
mailing list