[PATCH] mtd: spi-nor-ids: Add support for flashes tested by xilinx
Michal Simek
michal.simek at amd.com
Mon Jul 4 15:42:14 CEST 2022
On 5/25/22 07:17, Ashok Reddy Soma wrote:
> Add support for various flashes from below manufacturers which are tested
> by xilinx for years.
>
> EON:
> en25q128b
> GIGA:
> gd25lx256e
> ISSI:
> is25lp008
> is25lp016
> is25lp01g
> is25wp008
> is25wp016
> is25wp01g
> is25wx256
> MACRONIX:
> mx25u51245f
> mx66u1g45g
> mx66l2g45g
> MICRON:
> mt35xl512aba
> mt35xu01g
> SPANSION:
> s70fs01gs_256k
> SST:
> sst26wf016b
> WINBOND:
> w25q16dw
> w25q16jv
> w25q512jv
> w25q32bv
> w25h02jv
>
> Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma at xilinx.com>
> ---
>
> drivers/mtd/spi/spi-nor-ids.c | 37 +++++++++++++++++++++++++++++++++++
> 1 file changed, 37 insertions(+)
>
> diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
> index 7050ddc397..5d8bf05ff8 100644
> --- a/drivers/mtd/spi/spi-nor-ids.c
> +++ b/drivers/mtd/spi/spi-nor-ids.c
> @@ -82,6 +82,7 @@ const struct flash_info spi_nor_ids[] = {
> /* EON -- en25xxx */
> { INFO("en25q32b", 0x1c3016, 0, 64 * 1024, 64, 0) },
> { INFO("en25q64", 0x1c3017, 0, 64 * 1024, 128, SECT_4K) },
> + { INFO("en25q128b", 0x1c3018, 0, 64 * 1024, 256, 0) },
> { INFO("en25qh128", 0x1c7018, 0, 64 * 1024, 256, 0) },
> { INFO("en25s64", 0x1c3817, 0, 64 * 1024, 128, SECT_4K) },
> #endif
> @@ -127,11 +128,17 @@ const struct flash_info spi_nor_ids[] = {
> SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
> SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
> },
> + {
> + INFO("gd25lx256e", 0xc86819, 0, 64 * 1024, 512,
> + SECT_4K | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)
> + },
> #endif
> #ifdef CONFIG_SPI_FLASH_ISSI /* ISSI */
> /* ISSI */
> { INFO("is25lq040b", 0x9d4013, 0, 64 * 1024, 8,
> SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
> + { INFO("is25lp008", 0x9d6014, 0, 64 * 1024, 16, SPI_NOR_QUAD_READ) },
> + { INFO("is25lp016", 0x9d6015, 0, 64 * 1024, 32, SPI_NOR_QUAD_READ) },
> { INFO("is25lp032", 0x9d6016, 0, 64 * 1024, 64, 0) },
> { INFO("is25lp064", 0x9d6017, 0, 64 * 1024, 128, 0) },
> { INFO("is25lp128", 0x9d6018, 0, 64 * 1024, 256,
> @@ -140,6 +147,10 @@ const struct flash_info spi_nor_ids[] = {
> SECT_4K | SPI_NOR_DUAL_READ) },
> { INFO("is25lp512", 0x9d601a, 0, 64 * 1024, 1024,
> SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
> + { INFO("is25lp01g", 0x9d601b, 0, 64 * 1024, 2048,
> + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
> + { INFO("is25wp008", 0x9d7014, 0, 64 * 1024, 16, SPI_NOR_QUAD_READ) },
> + { INFO("is25wp016", 0x9d7015, 0, 64 * 1024, 32, SPI_NOR_QUAD_READ) },
> { INFO("is25wp032", 0x9d7016, 0, 64 * 1024, 64,
> SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
> { INFO("is25wp064", 0x9d7017, 0, 64 * 1024, 128,
> @@ -151,6 +162,10 @@ const struct flash_info spi_nor_ids[] = {
> SPI_NOR_4B_OPCODES) },
> { INFO("is25wp512", 0x9d701a, 0, 64 * 1024, 1024,
> SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
> + { INFO("is25wp01g", 0x9d701b, 0, 64 * 1024, 2048,
> + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
> + { INFO("is25wx256", 0x9d5b19, 0, 128 * 1024, 256,
> + SECT_4K | USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) },
> #endif
> #ifdef CONFIG_SPI_FLASH_MACRONIX /* MACRONIX */
> /* Macronix */
> @@ -176,8 +191,11 @@ const struct flash_info spi_nor_ids[] = {
> { INFO("mx25l25655e", 0xc22619, 0, 64 * 1024, 512, 0) },
> { INFO("mx66l51235l", 0xc2201a, 0, 64 * 1024, 1024, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
> { INFO("mx66u51235f", 0xc2253a, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
> + { INFO("mx25u51245f", 0xc2953a, 0, 64 * 1024, 1024, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
> + { INFO("mx66u1g45g", 0xc2253b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
> { INFO("mx66u2g45g", 0xc2253c, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
> { INFO("mx66l1g45g", 0xc2201b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
> + { INFO("mx66l2g45g", 0xc2201c, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
> { INFO("mx25l1633e", 0xc22415, 0, 64 * 1024, 32, SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | SECT_4K) },
> { INFO("mx25r6435f", 0xc22817, 0, 64 * 1024, 128, SECT_4K) },
> { INFO("mx66uw2g345g", 0xc2943c, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) },
> @@ -208,8 +226,10 @@ const struct flash_info spi_nor_ids[] = {
> { INFO("mt25qu02g", 0x20bb22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
> { INFO("mt25ql02g", 0x20ba22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE | SPI_NOR_4B_OPCODES) },
> #ifdef CONFIG_SPI_FLASH_MT35XU
> + { INFO("mt35xl512aba", 0x2c5a1a, 0, 128 * 1024, 512, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES | SPI_NOR_OCTAL_DTR_READ) },
> { INFO("mt35xu512aba", 0x2c5b1a, 0, 128 * 1024, 512, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES | SPI_NOR_OCTAL_DTR_READ) },
> #endif /* CONFIG_SPI_FLASH_MT35XU */
> + { INFO6("mt35xu01g", 0x2c5b1b, 0x104100, 128 * 1024, 1024, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) },
> { INFO("mt35xu02g", 0x2c5b1c, 0, 128 * 1024, 2048, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) },
> #endif
> #ifdef CONFIG_SPI_FLASH_SPANSION /* SPANSION */
> @@ -225,6 +245,7 @@ const struct flash_info spi_nor_ids[] = {
> { INFO("s25fl512s_256k", 0x010220, 0x4d00, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
> { INFO("s25fl512s_64k", 0x010220, 0x4d01, 64 * 1024, 1024, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
> { INFO("s25fl512s_512k", 0x010220, 0x4f00, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
> + { INFO("s70fs01gs_256k", 0x010221, 0x4d00, 256 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
> { INFO("s25sl12800", 0x012018, 0x0300, 256 * 1024, 64, 0) },
> { INFO("s25sl12801", 0x012018, 0x0301, 64 * 1024, 256, 0) },
> { INFO6("s25fl128s", 0x012018, 0x4d0180, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
> @@ -275,6 +296,7 @@ const struct flash_info spi_nor_ids[] = {
> { INFO("sst25wf040", 0xbf2504, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) },
> { INFO("sst25wf080", 0xbf2505, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) },
> { INFO("sst26vf064b", 0xbf2643, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_HAS_SST26LOCK | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
> + { INFO("sst26wf016b", 0xbf2641, 0, 64 * 1024, 32, SECT_4K) },
> { INFO("sst26wf016", 0xbf2651, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_HAS_SST26LOCK) },
> { INFO("sst26wf032", 0xbf2622, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_HAS_SST26LOCK) },
> { INFO("sst26wf064", 0xbf2643, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_HAS_SST26LOCK) },
> @@ -311,11 +333,19 @@ const struct flash_info spi_nor_ids[] = {
> { INFO("w25q20bw", 0xef5012, 0, 64 * 1024, 4, SECT_4K) },
> { INFO("w25q20ew", 0xef6012, 0, 64 * 1024, 4, SECT_4K) },
> { INFO("w25q32", 0xef4016, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
> + {
> + INFO("w25q16dw", 0xef6015, 0, 64 * 1024, 32,
> + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
> + },
> {
> INFO("w25q32dw", 0xef6016, 0, 64 * 1024, 64,
> SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
> SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
> },
> + {
> + INFO("w25q16jv", 0xef7015, 0, 64 * 1024, 32,
> + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
> + },
> {
> INFO("w25q32jv", 0xef7016, 0, 64 * 1024, 64,
> SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
> @@ -362,6 +392,11 @@ const struct flash_info spi_nor_ids[] = {
> SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
> SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
> },
> + {
> + INFO("w25q512jv", 0xef7119, 0, 64 * 1024, 512,
> + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
> + SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
> + },
> {
> INFO("w25q01jv", 0xef4021, 0, 64 * 1024, 2048,
> SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
> @@ -370,6 +405,7 @@ const struct flash_info spi_nor_ids[] = {
> { INFO("w25q80", 0xef5014, 0, 64 * 1024, 16, SECT_4K) },
> { INFO("w25q80bl", 0xef4014, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
> { INFO("w25q16cl", 0xef4015, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
> + { INFO("w25q32bv", 0xef4016, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
> { INFO("w25q64cv", 0xef4017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
> { INFO("w25q128", 0xef4018, 0, 64 * 1024, 256,
> SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
> @@ -378,6 +414,7 @@ const struct flash_info spi_nor_ids[] = {
> { INFO("w25q256", 0xef4019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
> { INFO("w25m512jw", 0xef6119, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
> { INFO("w25m512jv", 0xef7119, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
> + { INFO("w25h02jv", 0xef9022, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
> #endif
> #ifdef CONFIG_SPI_FLASH_XMC
> /* XMC (Wuhan Xinxin Semiconductor Manufacturing Corp.) */
fyi: This has been merged to next by Tom.
M
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