[PATCH v3 7/9] pinctrl: qcom: Add pinctrl driver for QCS404 SoC

[Sumit Garg]

Currently this pinctrl driver only supports BLSP UART2 specific pin
configuration.

Signed-off-by: Sumit Garg <sumit.garg at linaro.org>
Reviewed-by: Ramon Fried <rfried.dev at gmail.com>
---
 arch/arm/mach-snapdragon/Makefile             |  1 +
 arch/arm/mach-snapdragon/pinctrl-qcs404.c     | 55 +++++++++++++++++++
 arch/arm/mach-snapdragon/pinctrl-snapdragon.c |  1 +
 arch/arm/mach-snapdragon/pinctrl-snapdragon.h |  1 +
 4 files changed, 58 insertions(+)
 create mode 100644 arch/arm/mach-snapdragon/pinctrl-qcs404.c

diff --git a/arch/arm/mach-snapdragon/Makefile b/arch/arm/mach-snapdragon/Makefile
index 962855eb8c..cb8c1aa8d2 100644
--- a/arch/arm/mach-snapdragon/Makefile
+++ b/arch/arm/mach-snapdragon/Makefile
@@ -15,4 +15,5 @@ obj-y += dram.o
 obj-y += pinctrl-snapdragon.o
 obj-y += pinctrl-apq8016.o
 obj-y += pinctrl-apq8096.o
+obj-y += pinctrl-qcs404.o
 obj-$(CONFIG_SDM845) += pinctrl-sdm845.o
diff --git a/arch/arm/mach-snapdragon/pinctrl-qcs404.c b/arch/arm/mach-snapdragon/pinctrl-qcs404.c
new file mode 100644
index 0000000000..889ead0f57
--- /dev/null
+++ b/arch/arm/mach-snapdragon/pinctrl-qcs404.c
@@ -0,0 +1,55 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Qualcomm QCS404 pinctrl
+ *
+ * (C) Copyright 2022 Sumit Garg <sumit.garg at linaro.org>
+ */
+
+#include "pinctrl-snapdragon.h"
+#include <common.h>
+
+#define MAX_PIN_NAME_LEN 32
+static char pin_name[MAX_PIN_NAME_LEN] __section(".data");
+static const char * const msm_pinctrl_pins[] = {
+	"SDC1_RCLK",
+	"SDC1_CLK",
+	"SDC1_CMD",
+	"SDC1_DATA",
+	"SDC2_CLK",
+	"SDC2_CMD",
+	"SDC2_DATA",
+};
+
+static const struct pinctrl_function msm_pinctrl_functions[] = {
+	{"blsp_uart2", 1},
+};
+
+static const char *qcs404_get_function_name(struct udevice *dev,
+					    unsigned int selector)
+{
+	return msm_pinctrl_functions[selector].name;
+}
+
+static const char *qcs404_get_pin_name(struct udevice *dev,
+				       unsigned int selector)
+{
+	if (selector < 120) {
+		snprintf(pin_name, MAX_PIN_NAME_LEN, "GPIO_%u", selector);
+		return pin_name;
+	} else {
+		return msm_pinctrl_pins[selector - 120];
+	}
+}
+
+static unsigned int qcs404_get_function_mux(unsigned int selector)
+{
+	return msm_pinctrl_functions[selector].val;
+}
+
+struct msm_pinctrl_data qcs404_data = {
+	.pin_count = 126,
+	.functions_count = ARRAY_SIZE(msm_pinctrl_functions),
+	.get_function_name = qcs404_get_function_name,
+	.get_function_mux = qcs404_get_function_mux,
+	.get_pin_name = qcs404_get_pin_name,
+};
diff --git a/arch/arm/mach-snapdragon/pinctrl-snapdragon.c b/arch/arm/mach-snapdragon/pinctrl-snapdragon.c
index d1c560dd40..c2148a5d0a 100644
--- a/arch/arm/mach-snapdragon/pinctrl-snapdragon.c
+++ b/arch/arm/mach-snapdragon/pinctrl-snapdragon.c
@@ -119,6 +119,7 @@ static const struct udevice_id msm_pinctrl_ids[] = {
 #ifdef CONFIG_SDM845
 	{ .compatible = "qcom,tlmm-sdm845", .data = (ulong)&sdm845_data },
 #endif
+	{ .compatible = "qcom,tlmm-qcs404", .data = (ulong)&qcs404_data },
 	{ }
 };
 
diff --git a/arch/arm/mach-snapdragon/pinctrl-snapdragon.h b/arch/arm/mach-snapdragon/pinctrl-snapdragon.h
index ea524312a0..178ee01a41 100644
--- a/arch/arm/mach-snapdragon/pinctrl-snapdragon.h
+++ b/arch/arm/mach-snapdragon/pinctrl-snapdragon.h
@@ -28,5 +28,6 @@ struct pinctrl_function {
 extern struct msm_pinctrl_data apq8016_data;
 extern struct msm_pinctrl_data apq8096_data;
 extern struct msm_pinctrl_data sdm845_data;
+extern struct msm_pinctrl_data qcs404_data;
 
 #endif
-- 
2.25.1