[PATCH v5 3/7] configs: Add config for enabling FSPI boot option for i.MX8m

[Mamta Shukla]

Add imx8mm_evk_fspi_defconfig to build QSPI boot image.
This config is based on imx8mm_evk_defconfig with addtional config options for
FSPI Header,SPL offset and imx-image config to boot from FSPI.

Signed-off-by: Mamta Shukla <mamta.shukla at leica-geosystems.com>
Signed-off-by: Thomas Haemmerle <thomas.haemmerle at leica-geosystems.com>
Tested-by: Adam Ford <aford173 at gmail.com>
Reviewed-by: Fabio Estevam <festevam at denx.de>
Reviewed-by: Andrey Zhizhikin  <andrey.zhizhikin at leica-geosystems.com>
---
v2:
-Remove extra line in commit message
-Remove extra line in imx8mm_evk_fspi_defconfig
-New patch in series to add an entry for imx8mm_evk_fspi_defconfig in
board/freescale/imx8mm_evk/MAINTAINERS

v3:
-No changes

v4:
-No changes

v5:
-Remove  __ASSEMBLY__ as it has been dropped in commit 5c86a8f7a191 ("imx:
Don't define __ASSEMBLY__ in source files")
-Sync config with commit e092e3250270 ("Prepare v2022.07")

 .../imx8mm_evk/imximage-8mm-lpddr4-fspi.cfg   |   7 +
 configs/imx8mm_evk_fspi_defconfig             | 124 ++++++++++++++++++
 2 files changed, 131 insertions(+)
 create mode 100644 board/freescale/imx8mm_evk/imximage-8mm-lpddr4-fspi.cfg
 create mode 100644 configs/imx8mm_evk_fspi_defconfig

diff --git a/board/freescale/imx8mm_evk/imximage-8mm-lpddr4-fspi.cfg b/board/freescale/imx8mm_evk/imximage-8mm-lpddr4-fspi.cfg
new file mode 100644
index 0000000000..fcace8a93a
--- /dev/null
+++ b/board/freescale/imx8mm_evk/imximage-8mm-lpddr4-fspi.cfg
@@ -0,0 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2021 NXP
+ */
+
+BOOT_FROM	fspi
+LOADER		u-boot-spl-ddr.bin	0x7E2000
diff --git a/configs/imx8mm_evk_fspi_defconfig b/configs/imx8mm_evk_fspi_defconfig
new file mode 100644
index 0000000000..9610e4b334
--- /dev/null
+++ b/configs/imx8mm_evk_fspi_defconfig
@@ -0,0 +1,124 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_ENV_SIZE=0x1000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx8mm-evk"
+CONFIG_SPL_TEXT_BASE=0x7E2000
+CONFIG_TARGET_IMX8MM_EVK=y
+CONFIG_IMX_CONFIG="board/freescale/imx8mm_evk/imximage-8mm-lpddr4-fspi.cfg"
+CONFIG_SPL_MMC=y
+CONFIG_SPL_NOR_SUPPORT=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_SYS_LOAD_ADDR=0x40480000
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_SPL_MAX_SIZE=0x25000
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x910000
+CONFIG_SPL_BSS_MAX_SIZE=0x2000
+CONFIG_SPL_BOARD_INIT=y
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_STACK=0x920000
+CONFIG_SYS_SPL_MALLOC=y
+CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
+CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000
+CONFIG_SYS_SPL_MALLOC_SIZE=0x80000
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
+CONFIG_SPL_I2C=y
+CONFIG_SPL_POWER=y
+CONFIG_SPL_WATCHDOG=y
+CONFIG_SYS_PROMPT="u-boot=> "
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MAXARGS=64
+CONFIG_SYS_CBSIZE=2048
+CONFIG_SYS_PBSIZE=2074
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_CLK=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_USE_ETHPRIME=y
+CONFIG_ETHPRIME="FEC"
+CONFIG_SPL_DM=y
+CONFIG_SPL_CLK_COMPOSITE_CCF=y
+CONFIG_CLK_COMPOSITE_CCF=y
+CONFIG_SPL_CLK_IMX8MM=y
+CONFIG_CLK_IMX8MM=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_ES_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_FSL_USDHC=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_DM_PMIC=y
+CONFIG_SPL_DM_PMIC_PCA9450=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_PWM=y
+CONFIG_PWM_IMX=y
+CONFIG_DM_SERIAL=y
+CONFIG_MXC_UART=y
+CONFIG_SYSRESET=y
+CONFIG_SPL_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_SYSRESET_WATCHDOG=y
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_WATCHDOG=y
+CONFIG_NXP_FSPI=y
+CONFIG_SPI=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SF_DEFAULT_BUS=0
+CONFIG_SF_DEFAULT_CS=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SF_DEFAULT_MODE=0
+CONFIG_FSPI_CONF_HEADER=y
+CONFIG_FSPI_CONF_FILE="fspi_header.bin"
+CONFIG_READ_CLK_SOURCE=0x00
+CONFIG_DEVICE_TYPE=0x01
+CONFIG_FLASH_PAD_TYPE=0x01
+CONFIG_SERIAL_CLK_FREQUENCY=0x02
+CONFIG_LUT_CUSTOM_SEQUENCE=0x00
+CONFIG_LUT_SEQUENCE="0x0b, 0x04, 0x18, 0x08, 0x08, 0x30, 0x04, 0x24"
-- 
2.25.1