[PATCH v2 2/5] Add XTX SPI NOR 4MiB Flash chip in Rock Pi 4 boards from rev 1.4 on.

[Xavier Drudis Ferran]

Configure Rock Pi 4 to boot from SPI NOR Flash.

Based on flash chip, board documentation and tests, this is the
fastest I could use it.

This seems to be the minimum necessary configuration for Rock Pi 4 to
be able to boot from SPI NOR Flash.

With the next patch, it works to sf probe 1:0, sf read, sf erase, sf
write, sf read and then boot linux and flashrom can write to
it. Sometimes flashrom seems to fail to write when at U-Boot stage
there was no sf read or write, not sure why.

Changes from v1:
   - include CONFIG_SF_DEFAULT_BUS=1 now that numeration
     will be unified between U-Boot and SPL (at patch 5/5)

Signed-off-by: Xavier Drudis Ferran <xdrudis at tinet.cat>

Cc: Simon Glass <sjg at chromium.org>
Cc: Philipp Tomsich <philipp.tomsich at vrull.eu>
Cc: Kever Yang <kever.yang at rock-chips.com>
---
 arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi | 18 ++++++++++++++++++
 configs/rock-pi-4-rk3399_defconfig        | 22 ++++++++++++++++++++++
 2 files changed, 40 insertions(+)

diff --git a/arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi b/arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi
index c17e769f64..4c2fe8f6bc 100644
--- a/arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi
+++ b/arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi
@@ -15,3 +15,21 @@
 &vdd_log {
 	regulator-init-microvolt = <950000>;
 };
+
+&spi1 {
+	status = "okay";
+	spi-max-frequency = <40000000>;
+	spi-activate-delay = <12000>; /* 12 ms */
+
+	norflash: flash at 0 {
+		compatible = "rockchip,spidev", "jedec,spi-nor";
+		reg = <0>;
+
+		spi-max-frequency = <40000000>;
+		spi-cpha;
+		spi-cpol;
+
+		status = "okay";
+		u-boot,dm-pre-reloc;
+	};
+};
diff --git a/configs/rock-pi-4-rk3399_defconfig b/configs/rock-pi-4-rk3399_defconfig
index eb5778dc17..93a8d3fd23 100644
--- a/configs/rock-pi-4-rk3399_defconfig
+++ b/configs/rock-pi-4-rk3399_defconfig
@@ -13,6 +13,8 @@ CONFIG_BOOTSTAGE_STASH_ADDR=0x3fbd0000
 CONFIG_DEBUG_UART_BASE=0xFF1A0000
 CONFIG_DEBUG_UART_CLOCK=24000000
 CONFIG_ENV_OFFSET_REDUND=0x3e0000
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI=y
 CONFIG_SYS_LOAD_ADDR=0x800800
 CONFIG_DEBUG_UART=y
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
@@ -36,6 +38,11 @@ CONFIG_SPL_BSS_MAX_SIZE=0x2000
 CONFIG_SPL_STACK=0x400000
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
+CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_MTD=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0xb0000
 CONFIG_TPL=y
 CONFIG_CMD_BOOTZ=y
 CONFIG_CMD_GPT=y
@@ -57,21 +64,36 @@ CONFIG_MMC_DW=y
 CONFIG_MMC_DW_ROCKCHIP=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_SF_DEFAULT_BUS=1
+CONFIG_SF_DEFAULT_MODE=0x3
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPI_FLASH_SOFT_RESET=y
+CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=y
+CONFIG_SPI_FLASH_XTX=y
+CONFIG_SPI_FLASH_MTD=y
 CONFIG_DM_ETH=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_GMAC_ROCKCHIP=y
 CONFIG_NVME_PCI=y
 CONFIG_PCI=y
+CONFIG_SPL_PHY=y
 CONFIG_PHY_ROCKCHIP_INNO_USB2=y
 CONFIG_PHY_ROCKCHIP_TYPEC=y
+CONFIG_DM_PMIC_FAN53555=y
 CONFIG_PMIC_RK8XX=y
 CONFIG_REGULATOR_PWM=y
+CONFIG_SPL_REGULATOR_PWM=y
+CONFIG_DM_REGULATOR_GPIO=y
 CONFIG_REGULATOR_RK8XX=y
 CONFIG_PWM_ROCKCHIP=y
 CONFIG_RAM_RK3399_LPDDR4=y
 CONFIG_DM_RESET=y
 CONFIG_BAUDRATE=1500000
 CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_ROCKCHIP_SPI=y
 CONFIG_SYSRESET=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
-- 
2.20.1