[PATCH 1/2] spi: xilinx_spi: Add support for spi memory operations
Ashok Reddy Soma
ashok.reddy.soma at xilinx.com
Sat Jul 16 08:58:46 CEST 2022
From: T Karthik Reddy <t.karthik.reddy at xilinx.com>
Add support for spi memory operations for xilinx AXI qspi driver.
This provides an high-level interface to execute SPI memory
operations by the controller.
Remove existing spi transfer based implementation and use
spi memory based exec_op() implementation for qspi IO operations.
Simplified existing startup_block implementation.
Signed-off-by: T Karthik Reddy <t.karthik.reddy at xilinx.com>
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma at xilinx.com>
---
drivers/spi/xilinx_spi.c | 194 +++++++++++++++++++++++----------------
1 file changed, 116 insertions(+), 78 deletions(-)
diff --git a/drivers/spi/xilinx_spi.c b/drivers/spi/xilinx_spi.c
index b892cdae9b..09d4b01631 100644
--- a/drivers/spi/xilinx_spi.c
+++ b/drivers/spi/xilinx_spi.c
@@ -19,6 +19,7 @@
#include <log.h>
#include <malloc.h>
#include <spi.h>
+#include <spi-mem.h>
#include <asm/io.h>
#include <wait_bit.h>
#include <linux/bitops.h>
@@ -73,7 +74,7 @@
#define XILSPI_MAX_XFER_BITS 8
#define XILSPI_SPICR_DFLT_ON (SPICR_MANUAL_SS | SPICR_MASTER_MODE | \
- SPICR_SPE)
+ SPICR_SPE | SPICR_MASTER_INHIBIT)
#define XILSPI_SPICR_DFLT_OFF (SPICR_MASTER_INHIBIT | SPICR_MANUAL_SS)
#define XILINX_SPI_IDLE_VAL GENMASK(7, 0)
@@ -119,6 +120,15 @@ static int xilinx_spi_probe(struct udevice *bus)
writel(SPISSR_RESET_VALUE, ®s->srr);
+ /*
+ * Reset RX & TX FIFO
+ * Enable Manual Slave Select Assertion,
+ * Set SPI controller into master mode, and enable it
+ */
+ writel(SPICR_RXFIFO_RESEST | SPICR_TXFIFO_RESEST |
+ SPICR_MANUAL_SS | SPICR_MASTER_MODE | SPICR_SPE,
+ ®s->spicr);
+
return 0;
}
@@ -136,7 +146,10 @@ static void spi_cs_deactivate(struct udevice *dev)
struct udevice *bus = dev_get_parent(dev);
struct xilinx_spi_priv *priv = dev_get_priv(bus);
struct xilinx_spi_regs *regs = priv->regs;
+ u32 reg;
+ reg = readl(®s->spicr) | SPICR_RXFIFO_RESEST | SPICR_TXFIFO_RESEST;
+ writel(reg, ®s->spicr);
writel(SPISSR_OFF, ®s->spissr);
}
@@ -205,81 +218,24 @@ static u32 xilinx_spi_read_rxfifo(struct udevice *bus, u8 *rxp, u32 rxbytes)
return i;
}
-static void xilinx_spi_startup_block(struct udevice *dev, unsigned int bytes,
- const void *dout, void *din)
+static int start_transfer(struct spi_slave *spi, const void *dout, void *din, u32 len)
{
- struct udevice *bus = dev_get_parent(dev);
+ struct udevice *bus = spi->dev->parent;
struct xilinx_spi_priv *priv = dev_get_priv(bus);
struct xilinx_spi_regs *regs = priv->regs;
- struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
- const unsigned char *txp = dout;
- unsigned char *rxp = din;
- u32 reg;
- u32 txbytes = bytes;
- u32 rxbytes = bytes;
-
- /*
- * This loop runs two times. First time to send the command.
- * Second time to transfer data. After transferring data,
- * it sets txp to the initial value for the normal operation.
- */
- for ( ; priv->startup < 2; priv->startup++) {
- xilinx_spi_fill_txfifo(bus, txp, txbytes);
- reg = readl(®s->spicr) & ~SPICR_MASTER_INHIBIT;
+ u32 count, txbytes, rxbytes;
+ int reg, ret;
+ const unsigned char *txp = (const unsigned char *)dout;
+ unsigned char *rxp = (unsigned char *)din;
+
+ txbytes = len;
+ rxbytes = len;
+ while (txbytes || rxbytes) {
+ /* Disable master transaction */
+ reg = readl(®s->spicr) | SPICR_MASTER_INHIBIT;
writel(reg, ®s->spicr);
- xilinx_spi_read_rxfifo(bus, rxp, rxbytes);
- txp = din;
-
- if (priv->startup) {
- spi_cs_deactivate(dev);
- spi_cs_activate(dev, slave_plat->cs);
- txp = dout;
- }
- }
-}
-
-static int xilinx_spi_xfer(struct udevice *dev, unsigned int bitlen,
- const void *dout, void *din, unsigned long flags)
-{
- struct udevice *bus = dev_get_parent(dev);
- struct xilinx_spi_priv *priv = dev_get_priv(bus);
- struct xilinx_spi_regs *regs = priv->regs;
- struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
- /* assume spi core configured to do 8 bit transfers */
- unsigned int bytes = bitlen / XILSPI_MAX_XFER_BITS;
- const unsigned char *txp = dout;
- unsigned char *rxp = din;
- u32 txbytes = bytes;
- u32 rxbytes = bytes;
- u32 reg, count;
- int ret;
-
- debug("spi_xfer: bus:%i cs:%i bitlen:%i bytes:%i flags:%lx\n",
- dev_seq(bus), slave_plat->cs, bitlen, bytes, flags);
-
- if (bitlen == 0)
- goto done;
-
- if (bitlen % XILSPI_MAX_XFER_BITS) {
- printf("XILSPI warning: Not a multiple of %d bits\n",
- XILSPI_MAX_XFER_BITS);
- flags |= SPI_XFER_END;
- goto done;
- }
-
- if (flags & SPI_XFER_BEGIN)
- spi_cs_activate(dev, slave_plat->cs);
-
- /*
- * This is the work around for the startup block issue in
- * the spi controller. SPI clock is passing through STARTUP
- * block to FLASH. STARTUP block don't provide clock as soon
- * as QSPI provides command. So first command fails.
- */
- xilinx_spi_startup_block(dev, bytes, dout, din);
-
- while (txbytes && rxbytes) {
count = xilinx_spi_fill_txfifo(bus, txp, txbytes);
+ /* Enable master transaction */
reg = readl(®s->spicr) & ~SPICR_MASTER_INHIBIT;
writel(reg, ®s->spicr);
txbytes -= count;
@@ -293,21 +249,99 @@ static int xilinx_spi_xfer(struct udevice *dev, unsigned int bitlen,
return ret;
}
- debug("txbytes:0x%x,txp:0x%p\n", txbytes, txp);
+ reg = readl(®s->spicr) | SPICR_MASTER_INHIBIT;
+ writel(reg, ®s->spicr);
count = xilinx_spi_read_rxfifo(bus, rxp, rxbytes);
rxbytes -= count;
if (rxp)
rxp += count;
- debug("rxbytes:0x%x rxp:0x%p\n", rxbytes, rxp);
}
- done:
- if (flags & SPI_XFER_END)
- spi_cs_deactivate(dev);
-
return 0;
}
+static void xilinx_spi_startup_block(struct spi_slave *spi)
+{
+ struct dm_spi_slave_plat *slave_plat =
+ dev_get_parent_plat(spi->dev);
+ unsigned char txp;
+ unsigned char rxp[8];
+
+ /*
+ * Perform a dummy read as a work around for
+ * the startup block issue.
+ */
+ spi_cs_activate(spi->dev, slave_plat->cs);
+ txp = 0x9f;
+ start_transfer(spi, (void *)&txp, NULL, 1);
+
+ start_transfer(spi, NULL, (void *)rxp, 6);
+
+ spi_cs_deactivate(spi->dev);
+}
+
+static int xilinx_spi_mem_exec_op(struct spi_slave *spi,
+ const struct spi_mem_op *op)
+{
+ struct dm_spi_slave_plat *slave_plat =
+ dev_get_parent_plat(spi->dev);
+ static u32 startup;
+ u32 dummy_len, ret;
+
+ /*
+ * This is the work around for the startup block issue in
+ * the spi controller. SPI clock is passing through STARTUP
+ * block to FLASH. STARTUP block don't provide clock as soon
+ * as QSPI provides command. So first command fails.
+ */
+ if (!startup) {
+ xilinx_spi_startup_block(spi);
+ startup++;
+ }
+
+ spi_cs_activate(spi->dev, slave_plat->cs);
+
+ if (op->cmd.opcode) {
+ ret = start_transfer(spi, (void *)&op->cmd.opcode, NULL, 1);
+ if (ret)
+ goto done;
+ }
+ if (op->addr.nbytes) {
+ int i;
+ u8 addr_buf[4];
+
+ for (i = 0; i < op->addr.nbytes; i++)
+ addr_buf[i] = op->addr.val >>
+ (8 * (op->addr.nbytes - i - 1));
+
+ ret = start_transfer(spi, (void *)addr_buf, NULL,
+ op->addr.nbytes);
+ if (ret)
+ goto done;
+ }
+ if (op->dummy.nbytes) {
+ dummy_len = op->dummy.nbytes * op->data.buswidth;
+ ret = start_transfer(spi, NULL, NULL, dummy_len);
+ if (ret)
+ goto done;
+ }
+ if (op->data.nbytes) {
+ if (op->data.dir == SPI_MEM_DATA_IN) {
+ ret = start_transfer(spi, NULL,
+ op->data.buf.in, op->data.nbytes);
+ } else {
+ ret = start_transfer(spi, op->data.buf.out,
+ NULL, op->data.nbytes);
+ }
+ if (ret)
+ goto done;
+ }
+done:
+ spi_cs_deactivate(spi->dev);
+
+ return ret;
+}
+
static int xilinx_spi_set_speed(struct udevice *bus, uint speed)
{
struct xilinx_spi_priv *priv = dev_get_priv(bus);
@@ -343,12 +377,16 @@ static int xilinx_spi_set_mode(struct udevice *bus, uint mode)
return 0;
}
+static const struct spi_controller_mem_ops xilinx_spi_mem_ops = {
+ .exec_op = xilinx_spi_mem_exec_op,
+};
+
static const struct dm_spi_ops xilinx_spi_ops = {
.claim_bus = xilinx_spi_claim_bus,
.release_bus = xilinx_spi_release_bus,
- .xfer = xilinx_spi_xfer,
.set_speed = xilinx_spi_set_speed,
.set_mode = xilinx_spi_set_mode,
+ .mem_ops = &xilinx_spi_mem_ops,
};
static const struct udevice_id xilinx_spi_ids[] = {
--
2.17.1
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