[PATCH 2/6] pinctrl: sunxi: Add NAND pinmuxes
Michael Nazzareno Trimarchi
michael at amarulasolutions.com
Mon Jul 18 19:26:29 CEST 2022
Hi Andre
On Mon, Jul 18, 2022 at 6:20 PM Andre Przywara <andre.przywara at arm.com> wrote:
>
> On Wed, 13 Jul 2022 22:15:22 -0500
> Samuel Holland <samuel at sholland.org> wrote:
>
> Hi,
>
> > NAND is always at function 2 on port C.
>
> Indeed.
>
> >
> > Pin lists and mux values were taken from the Linux drivers.
>
> Compared against the manuals. I didn't bother the check the pin ranges (I
> think some additional CS pins were not covered by the comments), but that
> shouldn't matter anyways.
>
> Reviewed-by: Andre Przywara <andre.przywara at arm.com>
>
> > Signed-off-by: Samuel Holland <samuel at sholland.org>
>
> Cheers,
> Andre
>
> P.S.: I see that the A83T kernel pinctrl driver uses "nand" for *some* pins
> instead of "nand0", not sure if that should to be fixed, or if it's too
> late for that (not that NAND is mentioned at all in the A83T DT files ...)
>
Are you going to queue them all?
Michael
> > ---
> >
> > drivers/pinctrl/sunxi/pinctrl-sunxi.c | 13 +++++++++++++
> > 1 file changed, 13 insertions(+)
> >
> > diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
> > index 9ce2bc1b3afb..b10e3e7b0690 100644
> > --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
> > +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
> > @@ -268,6 +268,7 @@ static const struct sunxi_pinctrl_function sun4i_a10_pinctrl_functions[] = {
> > #endif
> > { "mmc2", 3 }, /* PC6-PC15 */
> > { "mmc3", 2 }, /* PI4-PI9 */
> > + { "nand0", 2 }, /* PC0-PC24 */
> > { "spi0", 3 }, /* PC0-PC2, PC23 */
> > #if IS_ENABLED(CONFIG_UART0_PORT_F)
> > { "uart0", 4 }, /* PF2-PF4 */
> > @@ -292,6 +293,7 @@ static const struct sunxi_pinctrl_function sun5i_a13_pinctrl_functions[] = {
> > { "mmc0", 2 }, /* PF0-PF5 */
> > { "mmc1", 2 }, /* PG3-PG8 */
> > { "mmc2", 3 }, /* PC6-PC15 */
> > + { "nand0", 2 }, /* PC0-PC19 */
> > { "spi0", 3 }, /* PC0-PC3 */
> > #if IS_ENABLED(CONFIG_UART0_PORT_F)
> > { "uart0", 4 }, /* PF2-PF4 */
> > @@ -318,6 +320,7 @@ static const struct sunxi_pinctrl_function sun6i_a31_pinctrl_functions[] = {
> > { "mmc1", 2 }, /* PG0-PG5 */
> > { "mmc2", 3 }, /* PC6-PC15, PC24 */
> > { "mmc3", 4 }, /* PC6-PC15, PC24 */
> > + { "nand0", 2 }, /* PC0-PC26 */
> > { "spi0", 3 }, /* PC0-PC2, PC27 */
> > #if IS_ENABLED(CONFIG_UART0_PORT_F)
> > { "uart0", 3 }, /* PF2-PF4 */
> > @@ -361,6 +364,7 @@ static const struct sunxi_pinctrl_function sun7i_a20_pinctrl_functions[] = {
> > { "mmc1", 4 }, /* PG0-PG5 */
> > #endif
> > { "mmc2", 3 }, /* PC5-PC15, PC24 */
> > + { "nand0", 2 }, /* PC0-PC24 */
> > { "spi0", 3 }, /* PC0-PC2, PC23 */
> > #if IS_ENABLED(CONFIG_UART0_PORT_F)
> > { "uart0", 4 }, /* PF2-PF4 */
> > @@ -384,6 +388,7 @@ static const struct sunxi_pinctrl_function sun8i_a23_pinctrl_functions[] = {
> > { "mmc0", 2 }, /* PF0-PF5 */
> > { "mmc1", 2 }, /* PG0-PG5 */
> > { "mmc2", 3 }, /* PC5-PC16 */
> > + { "nand0", 2 }, /* PC0-PC16 */
> > { "spi0", 3 }, /* PC0-PC3 */
> > #if IS_ENABLED(CONFIG_UART0_PORT_F)
> > { "uart0", 3 }, /* PF2-PF4 */
> > @@ -421,6 +426,7 @@ static const struct sunxi_pinctrl_function sun8i_a33_pinctrl_functions[] = {
> > { "mmc0", 2 }, /* PF0-PF5 */
> > { "mmc1", 2 }, /* PG0-PG5 */
> > { "mmc2", 3 }, /* PC5-PC16 */
> > + { "nand0", 2 }, /* PC0-PC16 */
> > { "spi0", 3 }, /* PC0-PC3 */
> > #if IS_ENABLED(CONFIG_UART0_PORT_F)
> > { "uart0", 3 }, /* PF2-PF4 */
> > @@ -447,6 +453,7 @@ static const struct sunxi_pinctrl_function sun8i_a83t_pinctrl_functions[] = {
> > { "mmc0", 2 }, /* PF0-PF5 */
> > { "mmc1", 2 }, /* PG0-PG5 */
> > { "mmc2", 3 }, /* PC5-PC16 */
> > + { "nand0", 2 }, /* PC0-PC18 */
> > { "spi0", 3 }, /* PC0-PC3 */
> > #if IS_ENABLED(CONFIG_UART0_PORT_F)
> > { "uart0", 3 }, /* PF2-PF4 */
> > @@ -487,6 +494,7 @@ static const struct sunxi_pinctrl_function sun8i_h3_pinctrl_functions[] = {
> > { "mmc0", 2 }, /* PF0-PF5 */
> > { "mmc1", 2 }, /* PG0-PG5 */
> > { "mmc2", 3 }, /* PC5-PC16 */
> > + { "nand0", 2 }, /* PC0-PC16 */
> > { "spi0", 3 }, /* PC0-PC3 */
> > #if IS_ENABLED(CONFIG_UART0_PORT_F)
> > { "uart0", 3 }, /* PF2-PF4 */
> > @@ -553,6 +561,7 @@ static const struct sunxi_pinctrl_function sun9i_a80_pinctrl_functions[] = {
> > { "mmc0", 2 }, /* PF0-PF5 */
> > { "mmc1", 2 }, /* PG0-PG5 */
> > { "mmc2", 3 }, /* PC6-PC16 */
> > + { "nand0", 2 }, /* PC0-PC18 */
> > { "spi0", 3 }, /* PC0-PC2, PC19 */
> > #if IS_ENABLED(CONFIG_UART0_PORT_F)
> > { "uart0", 4 }, /* PF2-PF4 */
> > @@ -592,6 +601,7 @@ static const struct sunxi_pinctrl_function sun50i_a64_pinctrl_functions[] = {
> > { "mmc0", 2 }, /* PF0-PF5 */
> > { "mmc1", 2 }, /* PG0-PG5 */
> > { "mmc2", 3 }, /* PC1-PC16 */
> > + { "nand0", 2 }, /* PC0-PC16 */
> > { "pwm", 2 }, /* PD22 */
> > { "spi0", 4 }, /* PC0-PC3 */
> > #if IS_ENABLED(CONFIG_UART0_PORT_F)
> > @@ -633,6 +643,7 @@ static const struct sunxi_pinctrl_function sun50i_h5_pinctrl_functions[] = {
> > { "mmc0", 2 }, /* PF0-PF5 */
> > { "mmc1", 2 }, /* PG0-PG5 */
> > { "mmc2", 3 }, /* PC1-PC16 */
> > + { "nand0", 2 }, /* PC0-PC16 */
> > { "spi0", 3 }, /* PC0-PC3 */
> > #if IS_ENABLED(CONFIG_UART0_PORT_F)
> > { "uart0", 3 }, /* PF2-PF4 */
> > @@ -659,6 +670,7 @@ static const struct sunxi_pinctrl_function sun50i_h6_pinctrl_functions[] = {
> > { "mmc0", 2 }, /* PF0-PF5 */
> > { "mmc1", 2 }, /* PG0-PG5 */
> > { "mmc2", 3 }, /* PC1-PC14 */
> > + { "nand0", 2 }, /* PC0-PC16 */
> > { "spi0", 4 }, /* PC0-PC7 */
> > #if IS_ENABLED(CONFIG_UART0_PORT_F)
> > { "uart0", 3 }, /* PF2-PF4 */
> > @@ -696,6 +708,7 @@ static const struct sunxi_pinctrl_function sun50i_h616_pinctrl_functions[] = {
> > { "mmc0", 2 }, /* PF0-PF5 */
> > { "mmc1", 2 }, /* PG0-PG5 */
> > { "mmc2", 3 }, /* PC0-PC16 */
> > + { "nand0", 2 }, /* PC0-PC16 */
> > { "spi0", 4 }, /* PC0-PC7, PC15-PC16 */
> > #if IS_ENABLED(CONFIG_UART0_PORT_F)
> > { "uart0", 3 }, /* PF2-PF4 */
>
--
Michael Nazzareno Trimarchi
Co-Founder & Chief Executive Officer
M. +39 347 913 2170
michael at amarulasolutions.com
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Joop Geesinkweg 125, 1114 AB, Amsterdam, NL
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