[PATCH 2/2] mvebu: uDPU: disable non-present peripherals
Stefan Roese
sr at denx.de
Thu Jul 21 14:27:40 CEST 2022
On 03.06.22 12:53, Robert Marko wrote:
> uDPU like eDPU does not expose SCSI based peripherals like SATA nor PCI
> and for sure it does not have the Intel E1000 PCI card.
>
> So, like for eDPU remove those from the defconfig.
>
> Signed-off-by: Robert Marko <robert.marko at sartura.hr>
Applied to u-boot-marvell/master
Thanks,
Stefan
> ---
> configs/uDPU_defconfig | 7 +------
> 1 file changed, 1 insertion(+), 6 deletions(-)
>
> diff --git a/configs/uDPU_defconfig b/configs/uDPU_defconfig
> index f7cd1a0589..ec7cda6a29 100644
> --- a/configs/uDPU_defconfig
> +++ b/configs/uDPU_defconfig
> @@ -12,7 +12,6 @@ CONFIG_DEFAULT_DEVICE_TREE="armada-3720-uDPU"
> CONFIG_DEBUG_UART_BASE=0xd0012000
> CONFIG_SYS_LOAD_ADDR=0x6000000
> CONFIG_DEBUG_UART=y
> -CONFIG_AHCI=y
> CONFIG_DISTRO_DEFAULTS=y
> # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
> CONFIG_FIT=y
> @@ -33,7 +32,6 @@ CONFIG_CMD_GPIO=y
> CONFIG_CMD_I2C=y
> CONFIG_CMD_MMC=y
> CONFIG_CMD_MTD=y
> -CONFIG_CMD_PCI=y
> CONFIG_CMD_SPI=y
> CONFIG_CMD_USB=y
> # CONFIG_CMD_SETEXPR is not set
> @@ -49,7 +47,6 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y
> CONFIG_ARP_TIMEOUT=200
> CONFIG_NET_RETRY_COUNT=50
> CONFIG_NET_RANDOM_ETHADDR=y
> -CONFIG_AHCI_MVEBU=y
> CONFIG_CLK=y
> CONFIG_CLK_MVEBU=y
> CONFIG_DM_I2C=y
> @@ -72,17 +69,15 @@ CONFIG_PHYLIB_10G=y
> CONFIG_PHY_MARVELL=y
> CONFIG_PHY_FIXED=y
> CONFIG_PHY_GIGE=y
> -CONFIG_E1000=y
> CONFIG_MVNETA=y
> CONFIG_MVMDIO=y
> -CONFIG_PCI=y
> -CONFIG_PCI_AARDVARK=y
> CONFIG_PHY=y
> CONFIG_MVEBU_COMPHY_SUPPORT=y
> CONFIG_PINCTRL=y
> CONFIG_PINCTRL_ARMADA_37XX=y
> CONFIG_DM_REGULATOR_FIXED=y
> CONFIG_DM_REGULATOR_GPIO=y
> +# CONFIG_SCSI is not set
> CONFIG_MVEBU_A3700_UART=y
> CONFIG_MVEBU_A3700_SPI=y
> CONFIG_SYSINFO=y
Viele Grüße,
Stefan Roese
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: sr at denx.de
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