[PATCH v12 03/13] fpga: xilinx: add bitstream flags to driver desc
Oleksandr Suvorov
oleksandr.suvorov at foundries.io
Fri Jul 22 16:16:04 CEST 2022
Store a set of supported bitstream types in xilinx_desc structure.
It will be used to determine whether an FPGA image is able to be
loaded with a given driver.
Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov at foundries.io>
Tested-by: Ricardo Salveti <ricardo at foundries.io>
Tested-by: Adrian Fiergolski <adrian.fiergolski at fastree3d.com>
---
(no changes since v10)
Changes in v10:
- move FPGA flags to macros;
- initialize xilinx_desc structs directly, removing *_DESC macros;
- initialize flags for mach-zynq;
arch/arm/mach-zynq/cpu.c | 1 +
board/xilinx/versal/board.c | 5 ++++-
board/xilinx/zynqmp/zynqmp.c | 5 ++++-
include/versalpl.h | 3 ---
include/xilinx.h | 4 ++++
include/zynqmppl.h | 3 +--
6 files changed, 14 insertions(+), 7 deletions(-)
diff --git a/arch/arm/mach-zynq/cpu.c b/arch/arm/mach-zynq/cpu.c
index 69b818f24b8..ac595ee0a27 100644
--- a/arch/arm/mach-zynq/cpu.c
+++ b/arch/arm/mach-zynq/cpu.c
@@ -22,6 +22,7 @@ xilinx_desc fpga = {
.family = xilinx_zynq,
.iface = devcfg,
.operations = &zynq_op,
+ .flags = FPGA_LEGACY,
};
#endif
diff --git a/board/xilinx/versal/board.c b/board/xilinx/versal/board.c
index 81663e0cd0e..d8f39be56c8 100644
--- a/board/xilinx/versal/board.c
+++ b/board/xilinx/versal/board.c
@@ -27,7 +27,10 @@
DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_FPGA_VERSALPL)
-static xilinx_desc versalpl = XILINX_VERSAL_DESC;
+static xilinx_desc versalpl = {
+ xilinx_versal, csu_dma, 1, &versal_op, 0, &versal_op, NULL,
+ FPGA_LEGACY
+};
#endif
int board_init(void)
diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c
index 106c3953e1f..3faa3a00fc9 100644
--- a/board/xilinx/zynqmp/zynqmp.c
+++ b/board/xilinx/zynqmp/zynqmp.c
@@ -48,7 +48,10 @@
DECLARE_GLOBAL_DATA_PTR;
#if CONFIG_IS_ENABLED(FPGA) && defined(CONFIG_FPGA_ZYNQMPPL)
-static xilinx_desc zynqmppl = XILINX_ZYNQMP_DESC;
+static xilinx_desc zynqmppl = {
+ xilinx_zynqmp, csu_dma, 1, &zynqmp_op, 0, &zynqmp_op, NULL,
+ ZYNQMP_FPGA_FLAGS
+};
#endif
int __maybe_unused psu_uboot_init(void)
diff --git a/include/versalpl.h b/include/versalpl.h
index b94c82e6e66..0cc101be2f8 100644
--- a/include/versalpl.h
+++ b/include/versalpl.h
@@ -14,7 +14,4 @@
extern struct xilinx_fpga_op versal_op;
-#define XILINX_VERSAL_DESC \
-{ xilinx_versal, csu_dma, 1, &versal_op, 0, &versal_op }
-
#endif /* _VERSALPL_H_ */
diff --git a/include/xilinx.h b/include/xilinx.h
index 362943bc717..d9e4b8da968 100644
--- a/include/xilinx.h
+++ b/include/xilinx.h
@@ -37,6 +37,9 @@ typedef enum { /* typedef xilinx_family */
max_xilinx_type /* insert all new types before this */
} xilinx_family; /* end, typedef xilinx_family */
+/* FPGA bitstream supported types */
+#define FPGA_LEGACY BIT(0)
+
typedef struct { /* typedef xilinx_desc */
xilinx_family family; /* part type */
xilinx_iface iface; /* interface type */
@@ -45,6 +48,7 @@ typedef struct { /* typedef xilinx_desc */
int cookie; /* implementation specific cookie */
struct xilinx_fpga_op *operations; /* operations */
char *name; /* device name in bitstream */
+ int flags; /* compatible flags */
} xilinx_desc; /* end, typedef xilinx_desc */
struct xilinx_fpga_op {
diff --git a/include/zynqmppl.h b/include/zynqmppl.h
index 35cfe17d444..8401a850afb 100644
--- a/include/zynqmppl.h
+++ b/include/zynqmppl.h
@@ -25,7 +25,6 @@
extern struct xilinx_fpga_op zynqmp_op;
-#define XILINX_ZYNQMP_DESC \
-{ xilinx_zynqmp, csu_dma, 1, &zynqmp_op, 0, &zynqmp_op }
+#define ZYNQMP_FPGA_FLAGS (FPGA_LEGACY)
#endif /* _ZYNQMPPL_H_ */
--
2.36.1
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