[PATCH 3/4] arm: mvebu: Synchronize armada-385.dtsi with Linux v5.20

[Stefan Roese]

On 27.07.22 14:47, Pali Rohár wrote:
> * Define PCIe interrupts
> 
> Signed-off-by: Pali Rohár <pali at kernel.org>

Applied to u-boot-marvell/master

Thanks,
Stefan

> ---
>   arch/arm/dts/armada-385.dtsi | 52 ++++++++++++++++++++++++++++++------
>   1 file changed, 44 insertions(+), 8 deletions(-)
> 
> diff --git a/arch/arm/dts/armada-385.dtsi b/arch/arm/dts/armada-385.dtsi
> index 581a7d9beac3..48072fc7fd4a 100644
> --- a/arch/arm/dts/armada-385.dtsi
> +++ b/arch/arm/dts/armada-385.dtsi
> @@ -69,17 +69,26 @@
>   				reg = <0x0800 0 0 0 0>;
>   				#address-cells = <3>;
>   				#size-cells = <2>;
> +				interrupt-names = "intx";
> +				interrupts-extended = <&gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
>   				#interrupt-cells = <1>;
>   				ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
>   					  0x81000000 0 0 0x81000000 0x1 0 1 0>;
>   				bus-range = <0x00 0xff>;
> -				interrupt-map-mask = <0 0 0 0>;
> -				interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
> +				interrupt-map-mask = <0 0 0 7>;
> +				interrupt-map = <0 0 0 1 &pcie1_intc 0>,
> +						<0 0 0 2 &pcie1_intc 1>,
> +						<0 0 0 3 &pcie1_intc 2>,
> +						<0 0 0 4 &pcie1_intc 3>;
>   				marvell,pcie-port = <0>;
>   				marvell,pcie-lane = <0>;
>   				clocks = <&gateclk 8>;
>   				resets = <&systemc 0 0>;
>   				status = "disabled";
> +				pcie1_intc: interrupt-controller {
> +					interrupt-controller;
> +					#interrupt-cells = <1>;
> +				};
>   			};
>   
>   			/* x1 port */
> @@ -89,17 +98,26 @@
>   				reg = <0x1000 0 0 0 0>;
>   				#address-cells = <3>;
>   				#size-cells = <2>;
> +				interrupt-names = "intx";
> +				interrupts-extended = <&gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
>   				#interrupt-cells = <1>;
>   				ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
>   					  0x81000000 0 0 0x81000000 0x2 0 1 0>;
>   				bus-range = <0x00 0xff>;
> -				interrupt-map-mask = <0 0 0 0>;
> -				interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
> +				interrupt-map-mask = <0 0 0 7>;
> +				interrupt-map = <0 0 0 1 &pcie2_intc 0>,
> +						<0 0 0 2 &pcie2_intc 1>,
> +						<0 0 0 3 &pcie2_intc 2>,
> +						<0 0 0 4 &pcie2_intc 3>;
>   				marvell,pcie-port = <1>;
>   				marvell,pcie-lane = <0>;
>   				clocks = <&gateclk 5>;
>   				resets = <&systemc 0 1>;
>   				status = "disabled";
> +				pcie2_intc: interrupt-controller {
> +					interrupt-controller;
> +					#interrupt-cells = <1>;
> +				};
>   			};
>   
>   			/* x1 port */
> @@ -109,17 +127,26 @@
>   				reg = <0x1800 0 0 0 0>;
>   				#address-cells = <3>;
>   				#size-cells = <2>;
> +				interrupt-names = "intx";
> +				interrupts-extended = <&gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
>   				#interrupt-cells = <1>;
>   				ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
>   					  0x81000000 0 0 0x81000000 0x3 0 1 0>;
>   				bus-range = <0x00 0xff>;
> -				interrupt-map-mask = <0 0 0 0>;
> -				interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
> +				interrupt-map-mask = <0 0 0 7>;
> +				interrupt-map = <0 0 0 1 &pcie3_intc 0>,
> +						<0 0 0 2 &pcie3_intc 1>,
> +						<0 0 0 3 &pcie3_intc 2>,
> +						<0 0 0 4 &pcie3_intc 3>;
>   				marvell,pcie-port = <2>;
>   				marvell,pcie-lane = <0>;
>   				clocks = <&gateclk 6>;
>   				resets = <&systemc 0 2>;
>   				status = "disabled";
> +				pcie3_intc: interrupt-controller {
> +					interrupt-controller;
> +					#interrupt-cells = <1>;
> +				};
>   			};
>   
>   			/*
> @@ -132,17 +159,26 @@
>   				reg = <0x2000 0 0 0 0>;
>   				#address-cells = <3>;
>   				#size-cells = <2>;
> +				interrupt-names = "intx";
> +				interrupts-extended = <&gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
>   				#interrupt-cells = <1>;
>   				ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
>   					  0x81000000 0 0 0x81000000 0x4 0 1 0>;
>   				bus-range = <0x00 0xff>;
> -				interrupt-map-mask = <0 0 0 0>;
> -				interrupt-map = <0 0 0 0 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
> +				interrupt-map-mask = <0 0 0 7>;
> +				interrupt-map = <0 0 0 1 &pcie4_intc 0>,
> +						<0 0 0 2 &pcie4_intc 1>,
> +						<0 0 0 3 &pcie4_intc 2>,
> +						<0 0 0 4 &pcie4_intc 3>;
>   				marvell,pcie-port = <3>;
>   				marvell,pcie-lane = <0>;
>   				clocks = <&gateclk 7>;
>   				resets = <&systemc 0 3>;
>   				status = "disabled";
> +				pcie4_intc: interrupt-controller {
> +					interrupt-controller;
> +					#interrupt-cells = <1>;
> +				};
>   			};
>   		};
>   	};

Viele Grüße,
Stefan Roese

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