[PATCH 0/1] sunxi: support half DQ width memory on R40

[Evgeny Boger]

On Allwinner boards memory configuration is detected by bootloader.
However, R40 (A40i/T3) is somewhat unique because the detection by
the DRAM controller via PIR_QSGATE is broken (either in U-Boot or
in the controller). So the memory configuration must be detected
by other means.

Dual rank detection has been already implemented by Icenowy earlier.
This patch extends the automation detection so it can detect half-width
DQ configuration (i.e. single x16 DDR3 IC).

Tested on Allwinner A40i-based Wiren Board 7 automation controller,
for the following memory configurations:
* 1x 16-bit 4Gbit DDR3, 512 MiB total RAM
* 2x 16-bit 4Gbit DDR3, 1024 MiB total RAM
* 2x 16-bit 8Gbit DDR3, 2048 MiB total RAM

Unfortunately it has NOT been tested with dual-rank configuration yet,
as I don't have any dual-rank boards at hand.
I will really appreciate if someone could help me with that.

Evgeny Boger (1):
  sunxi: support half DQ width memory on R40

 .../include/asm/arch-sunxi/dram_sunxi_dw.h    |   1 +
 arch/arm/mach-sunxi/dram_sunxi_dw.c           | 115 ++++++++++++------
 2 files changed, 79 insertions(+), 37 deletions(-)

-- 
2.25.1