[PATCH 13/13] Convert CONFIG_SYS_DDR_RAW_TIMING to Kconfig

Tom Rini trini at konsulko.com
Wed Jun 15 18:03:55 CEST 2022 

This converts the following to Kconfig:
   CONFIG_SYS_DDR_RAW_TIMING

Signed-off-by: Tom Rini <trini at konsulko.com>
---
 README                                       | 6 ------
 configs/P1010RDB-PA_36BIT_NAND_defconfig     | 1 +
 configs/P1010RDB-PA_36BIT_NOR_defconfig      | 1 +
 configs/P1010RDB-PA_36BIT_SDCARD_defconfig   | 1 +
 configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig | 1 +
 configs/P1010RDB-PA_NAND_defconfig           | 1 +
 configs/P1010RDB-PA_NOR_defconfig            | 1 +
 configs/P1010RDB-PA_SDCARD_defconfig         | 1 +
 configs/P1010RDB-PA_SPIFLASH_defconfig       | 1 +
 configs/P1010RDB-PB_36BIT_NAND_defconfig     | 1 +
 configs/P1010RDB-PB_36BIT_NOR_defconfig      | 1 +
 configs/P1010RDB-PB_36BIT_SDCARD_defconfig   | 1 +
 configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig | 1 +
 configs/P1010RDB-PB_NAND_defconfig           | 1 +
 configs/P1010RDB-PB_NOR_defconfig            | 1 +
 configs/P1010RDB-PB_SDCARD_defconfig         | 1 +
 configs/P1010RDB-PB_SPIFLASH_defconfig       | 1 +
 configs/P1020RDB-PC_36BIT_NAND_defconfig     | 1 +
 configs/P1020RDB-PC_36BIT_SDCARD_defconfig   | 1 +
 configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig | 1 +
 configs/P1020RDB-PC_36BIT_defconfig          | 1 +
 configs/P1020RDB-PC_NAND_defconfig           | 1 +
 configs/P1020RDB-PC_SDCARD_defconfig         | 1 +
 configs/P1020RDB-PC_SPIFLASH_defconfig       | 1 +
 configs/P1020RDB-PC_defconfig                | 1 +
 configs/P1020RDB-PD_NAND_defconfig           | 1 +
 configs/P1020RDB-PD_SDCARD_defconfig         | 1 +
 configs/P1020RDB-PD_SPIFLASH_defconfig       | 1 +
 configs/P1020RDB-PD_defconfig                | 1 +
 configs/P2020RDB-PC_36BIT_NAND_defconfig     | 1 +
 configs/P2020RDB-PC_36BIT_SDCARD_defconfig   | 1 +
 configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig | 1 +
 configs/P2020RDB-PC_36BIT_defconfig          | 1 +
 configs/P2020RDB-PC_NAND_defconfig           | 1 +
 configs/P2020RDB-PC_SDCARD_defconfig         | 1 +
 configs/P2020RDB-PC_SPIFLASH_defconfig       | 1 +
 configs/P2020RDB-PC_defconfig                | 1 +
 configs/ls1021aqds_nand_defconfig            | 1 +
 configs/ls1021aqds_nor_SECURE_BOOT_defconfig | 1 +
 configs/ls1021aqds_nor_defconfig             | 1 +
 configs/ls1021aqds_nor_lpuart_defconfig      | 1 +
 configs/ls1021aqds_qspi_defconfig            | 1 +
 configs/ls1021aqds_sdcard_ifc_defconfig      | 1 +
 configs/ls1021aqds_sdcard_qspi_defconfig     | 1 +
 configs/ls1043ardb_SECURE_BOOT_defconfig     | 1 +
 configs/ls1043ardb_defconfig                 | 1 +
 configs/ls1043ardb_tfa_SECURE_BOOT_defconfig | 1 +
 configs/ls1043ardb_tfa_defconfig             | 1 +
 drivers/ddr/fsl/Kconfig                      | 7 +++++++
 include/configs/P1010RDB.h                   | 1 -
 include/configs/T102xRDB.h                   | 1 -
 include/configs/ls1021aqds.h                 | 4 ----
 include/configs/ls1043ardb.h                 | 1 -
 include/configs/ls2080a_common.h             | 4 ----
 include/configs/p1_p2_rdb_pc.h               | 1 -
 55 files changed, 54 insertions(+), 18 deletions(-)

diff --git a/README b/README
index 50a326a12426..a8d43f63b7e3 100644
--- a/README
+++ b/README
@@ -2079,12 +2079,6 @@ Low Level (hardware related) configuration options:
 		one, specify here. Note that the value must resolve
 		to something your driver can deal with.
 
-- CONFIG_SYS_DDR_RAW_TIMING
-		Get DDR timing information from other than SPD. Common with
-		soldered DDR chips onboard without SPD. DDR raw timing
-		parameters are extracted from datasheet and hard-coded into
-		header files or board specific files.
-
 - CONFIG_FSL_DDR_INTERACTIVE
 		Enable interactive DDR debugging. See doc/README.fsl-ddr.
 
diff --git a/configs/P1010RDB-PA_36BIT_NAND_defconfig b/configs/P1010RDB-PA_36BIT_NAND_defconfig
index c8f7e405d45e..607278434c4c 100644
--- a/configs/P1010RDB-PA_36BIT_NAND_defconfig
+++ b/configs/P1010RDB-PA_36BIT_NAND_defconfig
@@ -83,6 +83,7 @@ CONFIG_FSL_CAAM=y
 CONFIG_DDR_CLK_FREQ=66666666
 CONFIG_SYS_SPD_BUS_NUM=1
 CONFIG_CHIP_SELECTS_PER_CTRL=1
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_TPL_COMMON_INIT_DDR=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
diff --git a/configs/P1010RDB-PA_36BIT_NOR_defconfig b/configs/P1010RDB-PA_36BIT_NOR_defconfig
index 8d999b6375d2..81bfd7ae518c 100644
--- a/configs/P1010RDB-PA_36BIT_NOR_defconfig
+++ b/configs/P1010RDB-PA_36BIT_NOR_defconfig
@@ -50,6 +50,7 @@ CONFIG_FSL_CAAM=y
 CONFIG_DDR_CLK_FREQ=66666666
 CONFIG_SYS_SPD_BUS_NUM=1
 CONFIG_CHIP_SELECTS_PER_CTRL=1
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_COMMON_INIT_DDR=y
 CONFIG_SPL_COMMON_INIT_DDR=y
 CONFIG_DM_I2C=y
diff --git a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig
index d9bf749bc505..1ebfdec719e8 100644
--- a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig
+++ b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig
@@ -72,6 +72,7 @@ CONFIG_FSL_CAAM=y
 CONFIG_DDR_CLK_FREQ=66666666
 CONFIG_SYS_SPD_BUS_NUM=1
 CONFIG_CHIP_SELECTS_PER_CTRL=1
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_SPL_COMMON_INIT_DDR=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
diff --git a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig
index d4c3899596b4..f2bef4774ede 100644
--- a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig
+++ b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig
@@ -75,6 +75,7 @@ CONFIG_FSL_CAAM=y
 CONFIG_DDR_CLK_FREQ=66666666
 CONFIG_SYS_SPD_BUS_NUM=1
 CONFIG_CHIP_SELECTS_PER_CTRL=1
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_SPL_COMMON_INIT_DDR=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
diff --git a/configs/P1010RDB-PA_NAND_defconfig b/configs/P1010RDB-PA_NAND_defconfig
index dd08b8c9725f..373333dcc3c1 100644
--- a/configs/P1010RDB-PA_NAND_defconfig
+++ b/configs/P1010RDB-PA_NAND_defconfig
@@ -82,6 +82,7 @@ CONFIG_FSL_CAAM=y
 CONFIG_DDR_CLK_FREQ=66666666
 CONFIG_SYS_SPD_BUS_NUM=1
 CONFIG_CHIP_SELECTS_PER_CTRL=1
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_TPL_COMMON_INIT_DDR=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
diff --git a/configs/P1010RDB-PA_NOR_defconfig b/configs/P1010RDB-PA_NOR_defconfig
index 92396208b273..9240c38c164a 100644
--- a/configs/P1010RDB-PA_NOR_defconfig
+++ b/configs/P1010RDB-PA_NOR_defconfig
@@ -49,6 +49,7 @@ CONFIG_FSL_CAAM=y
 CONFIG_DDR_CLK_FREQ=66666666
 CONFIG_SYS_SPD_BUS_NUM=1
 CONFIG_CHIP_SELECTS_PER_CTRL=1
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_COMMON_INIT_DDR=y
 CONFIG_SPL_COMMON_INIT_DDR=y
 CONFIG_DM_I2C=y
diff --git a/configs/P1010RDB-PA_SDCARD_defconfig b/configs/P1010RDB-PA_SDCARD_defconfig
index 85c0e83aee77..c0fa3b5e4eb3 100644
--- a/configs/P1010RDB-PA_SDCARD_defconfig
+++ b/configs/P1010RDB-PA_SDCARD_defconfig
@@ -71,6 +71,7 @@ CONFIG_FSL_CAAM=y
 CONFIG_DDR_CLK_FREQ=66666666
 CONFIG_SYS_SPD_BUS_NUM=1
 CONFIG_CHIP_SELECTS_PER_CTRL=1
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_SPL_COMMON_INIT_DDR=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
diff --git a/configs/P1010RDB-PA_SPIFLASH_defconfig b/configs/P1010RDB-PA_SPIFLASH_defconfig
index 5ead2a86eaff..4affbf52cc96 100644
--- a/configs/P1010RDB-PA_SPIFLASH_defconfig
+++ b/configs/P1010RDB-PA_SPIFLASH_defconfig
@@ -74,6 +74,7 @@ CONFIG_FSL_CAAM=y
 CONFIG_DDR_CLK_FREQ=66666666
 CONFIG_SYS_SPD_BUS_NUM=1
 CONFIG_CHIP_SELECTS_PER_CTRL=1
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_SPL_COMMON_INIT_DDR=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
diff --git a/configs/P1010RDB-PB_36BIT_NAND_defconfig b/configs/P1010RDB-PB_36BIT_NAND_defconfig
index b3a894d76c00..034bec111659 100644
--- a/configs/P1010RDB-PB_36BIT_NAND_defconfig
+++ b/configs/P1010RDB-PB_36BIT_NAND_defconfig
@@ -84,6 +84,7 @@ CONFIG_FSL_CAAM=y
 CONFIG_DDR_CLK_FREQ=66666666
 CONFIG_SYS_SPD_BUS_NUM=1
 CONFIG_CHIP_SELECTS_PER_CTRL=1
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_TPL_COMMON_INIT_DDR=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
diff --git a/configs/P1010RDB-PB_36BIT_NOR_defconfig b/configs/P1010RDB-PB_36BIT_NOR_defconfig
index 8bbff122f1c3..0a3ba0573e01 100644
--- a/configs/P1010RDB-PB_36BIT_NOR_defconfig
+++ b/configs/P1010RDB-PB_36BIT_NOR_defconfig
@@ -51,6 +51,7 @@ CONFIG_FSL_CAAM=y
 CONFIG_DDR_CLK_FREQ=66666666
 CONFIG_SYS_SPD_BUS_NUM=1
 CONFIG_CHIP_SELECTS_PER_CTRL=1
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_COMMON_INIT_DDR=y
 CONFIG_SPL_COMMON_INIT_DDR=y
 CONFIG_DM_I2C=y
diff --git a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig
index 9d2b55be8ec5..3e5d313c405f 100644
--- a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig
+++ b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig
@@ -73,6 +73,7 @@ CONFIG_FSL_CAAM=y
 CONFIG_DDR_CLK_FREQ=66666666
 CONFIG_SYS_SPD_BUS_NUM=1
 CONFIG_CHIP_SELECTS_PER_CTRL=1
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_SPL_COMMON_INIT_DDR=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
diff --git a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig
index fb0a6cfb0216..d28d037ff726 100644
--- a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig
+++ b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig
@@ -76,6 +76,7 @@ CONFIG_FSL_CAAM=y
 CONFIG_DDR_CLK_FREQ=66666666
 CONFIG_SYS_SPD_BUS_NUM=1
 CONFIG_CHIP_SELECTS_PER_CTRL=1
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_SPL_COMMON_INIT_DDR=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
diff --git a/configs/P1010RDB-PB_NAND_defconfig b/configs/P1010RDB-PB_NAND_defconfig
index 380b6596843e..a1e8d54c8c0e 100644
--- a/configs/P1010RDB-PB_NAND_defconfig
+++ b/configs/P1010RDB-PB_NAND_defconfig
@@ -83,6 +83,7 @@ CONFIG_FSL_CAAM=y
 CONFIG_DDR_CLK_FREQ=66666666
 CONFIG_SYS_SPD_BUS_NUM=1
 CONFIG_CHIP_SELECTS_PER_CTRL=1
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_TPL_COMMON_INIT_DDR=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
diff --git a/configs/P1010RDB-PB_NOR_defconfig b/configs/P1010RDB-PB_NOR_defconfig
index 4ce8b5e40eb3..af65061a0c3e 100644
--- a/configs/P1010RDB-PB_NOR_defconfig
+++ b/configs/P1010RDB-PB_NOR_defconfig
@@ -50,6 +50,7 @@ CONFIG_FSL_CAAM=y
 CONFIG_DDR_CLK_FREQ=66666666
 CONFIG_SYS_SPD_BUS_NUM=1
 CONFIG_CHIP_SELECTS_PER_CTRL=1
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_COMMON_INIT_DDR=y
 CONFIG_SPL_COMMON_INIT_DDR=y
 CONFIG_DM_I2C=y
diff --git a/configs/P1010RDB-PB_SDCARD_defconfig b/configs/P1010RDB-PB_SDCARD_defconfig
index 7c02d40aa246..36892c9fc2e4 100644
--- a/configs/P1010RDB-PB_SDCARD_defconfig
+++ b/configs/P1010RDB-PB_SDCARD_defconfig
@@ -72,6 +72,7 @@ CONFIG_FSL_CAAM=y
 CONFIG_DDR_CLK_FREQ=66666666
 CONFIG_SYS_SPD_BUS_NUM=1
 CONFIG_CHIP_SELECTS_PER_CTRL=1
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_SPL_COMMON_INIT_DDR=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
diff --git a/configs/P1010RDB-PB_SPIFLASH_defconfig b/configs/P1010RDB-PB_SPIFLASH_defconfig
index 378a4e6f6091..381c1d3bb96a 100644
--- a/configs/P1010RDB-PB_SPIFLASH_defconfig
+++ b/configs/P1010RDB-PB_SPIFLASH_defconfig
@@ -75,6 +75,7 @@ CONFIG_FSL_CAAM=y
 CONFIG_DDR_CLK_FREQ=66666666
 CONFIG_SYS_SPD_BUS_NUM=1
 CONFIG_CHIP_SELECTS_PER_CTRL=1
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_SPL_COMMON_INIT_DDR=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
diff --git a/configs/P1020RDB-PC_36BIT_NAND_defconfig b/configs/P1020RDB-PC_36BIT_NAND_defconfig
index 436bc1d64b26..663c3bcdbc9d 100644
--- a/configs/P1020RDB-PC_36BIT_NAND_defconfig
+++ b/configs/P1020RDB-PC_36BIT_NAND_defconfig
@@ -81,6 +81,7 @@ CONFIG_LBA48=y
 CONFIG_DDR_CLK_FREQ=66666666
 CONFIG_SYS_SPD_BUS_NUM=1
 CONFIG_CHIP_SELECTS_PER_CTRL=1
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_SYS_BR0_PRELIM_BOOL=y
 CONFIG_SYS_BR0_PRELIM=0xFF800C21
 CONFIG_SYS_OR0_PRELIM=0xFFFF8396
diff --git a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig
index 27d319048893..6c4575367be2 100644
--- a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig
+++ b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig
@@ -71,6 +71,7 @@ CONFIG_LBA48=y
 CONFIG_DDR_CLK_FREQ=66666666
 CONFIG_SYS_SPD_BUS_NUM=1
 CONFIG_CHIP_SELECTS_PER_CTRL=1
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_SYS_BR0_PRELIM_BOOL=y
 CONFIG_SYS_BR0_PRELIM=0xEF001001
 CONFIG_SYS_OR0_PRELIM=0xFC000FF7
diff --git a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig
index a32afb126052..b6d3dc95a692 100644
--- a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig
+++ b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig
@@ -74,6 +74,7 @@ CONFIG_LBA48=y
 CONFIG_DDR_CLK_FREQ=66666666
 CONFIG_SYS_SPD_BUS_NUM=1
 CONFIG_CHIP_SELECTS_PER_CTRL=1
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_SYS_BR0_PRELIM_BOOL=y
 CONFIG_SYS_BR0_PRELIM=0xEF001001
 CONFIG_SYS_OR0_PRELIM=0xFC000FF7
diff --git a/configs/P1020RDB-PC_36BIT_defconfig b/configs/P1020RDB-PC_36BIT_defconfig
index b74ec9749fe2..0130ce6cb661 100644
--- a/configs/P1020RDB-PC_36BIT_defconfig
+++ b/configs/P1020RDB-PC_36BIT_defconfig
@@ -50,6 +50,7 @@ CONFIG_LBA48=y
 CONFIG_DDR_CLK_FREQ=66666666
 CONFIG_SYS_SPD_BUS_NUM=1
 CONFIG_CHIP_SELECTS_PER_CTRL=1
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_SYS_BR0_PRELIM_BOOL=y
 CONFIG_SYS_BR0_PRELIM=0xEF001001
 CONFIG_SYS_OR0_PRELIM=0xFC000FF7
diff --git a/configs/P1020RDB-PC_NAND_defconfig b/configs/P1020RDB-PC_NAND_defconfig
index 76f7bc38bea7..fc32e89cf2af 100644
--- a/configs/P1020RDB-PC_NAND_defconfig
+++ b/configs/P1020RDB-PC_NAND_defconfig
@@ -80,6 +80,7 @@ CONFIG_LBA48=y
 CONFIG_DDR_CLK_FREQ=66666666
 CONFIG_SYS_SPD_BUS_NUM=1
 CONFIG_CHIP_SELECTS_PER_CTRL=1
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_SYS_BR0_PRELIM_BOOL=y
 CONFIG_SYS_BR0_PRELIM=0xFF800C21
 CONFIG_SYS_OR0_PRELIM=0xFFFF8396
diff --git a/configs/P1020RDB-PC_SDCARD_defconfig b/configs/P1020RDB-PC_SDCARD_defconfig
index 9cbf65b6dc22..6b6b12eae624 100644
--- a/configs/P1020RDB-PC_SDCARD_defconfig
+++ b/configs/P1020RDB-PC_SDCARD_defconfig
@@ -70,6 +70,7 @@ CONFIG_LBA48=y
 CONFIG_DDR_CLK_FREQ=66666666
 CONFIG_SYS_SPD_BUS_NUM=1
 CONFIG_CHIP_SELECTS_PER_CTRL=1
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_SYS_BR0_PRELIM_BOOL=y
 CONFIG_SYS_BR0_PRELIM=0xEF001001
 CONFIG_SYS_OR0_PRELIM=0xFC000FF7
diff --git a/configs/P1020RDB-PC_SPIFLASH_defconfig b/configs/P1020RDB-PC_SPIFLASH_defconfig
index 9215acdf5e9f..904658bd01b3 100644
--- a/configs/P1020RDB-PC_SPIFLASH_defconfig
+++ b/configs/P1020RDB-PC_SPIFLASH_defconfig
@@ -73,6 +73,7 @@ CONFIG_LBA48=y
 CONFIG_DDR_CLK_FREQ=66666666
 CONFIG_SYS_SPD_BUS_NUM=1
 CONFIG_CHIP_SELECTS_PER_CTRL=1
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_SYS_BR0_PRELIM_BOOL=y
 CONFIG_SYS_BR0_PRELIM=0xEF001001
 CONFIG_SYS_OR0_PRELIM=0xFC000FF7
diff --git a/configs/P1020RDB-PC_defconfig b/configs/P1020RDB-PC_defconfig
index ebd83e5ecb18..643cee0b24ca 100644
--- a/configs/P1020RDB-PC_defconfig
+++ b/configs/P1020RDB-PC_defconfig
@@ -49,6 +49,7 @@ CONFIG_LBA48=y
 CONFIG_DDR_CLK_FREQ=66666666
 CONFIG_SYS_SPD_BUS_NUM=1
 CONFIG_CHIP_SELECTS_PER_CTRL=1
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_SYS_BR0_PRELIM_BOOL=y
 CONFIG_SYS_BR0_PRELIM=0xEF001001
 CONFIG_SYS_OR0_PRELIM=0xFC000FF7
diff --git a/configs/P1020RDB-PD_NAND_defconfig b/configs/P1020RDB-PD_NAND_defconfig
index 5e2f3ccb86b3..5cec7f7bfc1b 100644
--- a/configs/P1020RDB-PD_NAND_defconfig
+++ b/configs/P1020RDB-PD_NAND_defconfig
@@ -83,6 +83,7 @@ CONFIG_LBA48=y
 CONFIG_DDR_CLK_FREQ=66666666
 CONFIG_SYS_SPD_BUS_NUM=1
 CONFIG_CHIP_SELECTS_PER_CTRL=2
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_SYS_BR0_PRELIM_BOOL=y
 CONFIG_SYS_BR0_PRELIM=0xFF800C21
 CONFIG_SYS_OR0_PRELIM=0xFFFF8796
diff --git a/configs/P1020RDB-PD_SDCARD_defconfig b/configs/P1020RDB-PD_SDCARD_defconfig
index 0e6531192503..c488aae69d5d 100644
--- a/configs/P1020RDB-PD_SDCARD_defconfig
+++ b/configs/P1020RDB-PD_SDCARD_defconfig
@@ -73,6 +73,7 @@ CONFIG_LBA48=y
 CONFIG_DDR_CLK_FREQ=66666666
 CONFIG_SYS_SPD_BUS_NUM=1
 CONFIG_CHIP_SELECTS_PER_CTRL=2
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_SYS_BR0_PRELIM_BOOL=y
 CONFIG_SYS_BR0_PRELIM=0xEC001001
 CONFIG_SYS_OR0_PRELIM=0xFC000FF7
diff --git a/configs/P1020RDB-PD_SPIFLASH_defconfig b/configs/P1020RDB-PD_SPIFLASH_defconfig
index f98fcd602ff9..78f680644a78 100644
--- a/configs/P1020RDB-PD_SPIFLASH_defconfig
+++ b/configs/P1020RDB-PD_SPIFLASH_defconfig
@@ -76,6 +76,7 @@ CONFIG_LBA48=y
 CONFIG_DDR_CLK_FREQ=66666666
 CONFIG_SYS_SPD_BUS_NUM=1
 CONFIG_CHIP_SELECTS_PER_CTRL=2
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_SYS_BR0_PRELIM_BOOL=y
 CONFIG_SYS_BR0_PRELIM=0xEC001001
 CONFIG_SYS_OR0_PRELIM=0xFC000FF7
diff --git a/configs/P1020RDB-PD_defconfig b/configs/P1020RDB-PD_defconfig
index a1cffb7c8457..40b6afa6cc0f 100644
--- a/configs/P1020RDB-PD_defconfig
+++ b/configs/P1020RDB-PD_defconfig
@@ -52,6 +52,7 @@ CONFIG_LBA48=y
 CONFIG_DDR_CLK_FREQ=66666666
 CONFIG_SYS_SPD_BUS_NUM=1
 CONFIG_CHIP_SELECTS_PER_CTRL=2
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_SYS_BR0_PRELIM_BOOL=y
 CONFIG_SYS_BR0_PRELIM=0xEC001001
 CONFIG_SYS_OR0_PRELIM=0xFC000FF7
diff --git a/configs/P2020RDB-PC_36BIT_NAND_defconfig b/configs/P2020RDB-PC_36BIT_NAND_defconfig
index 48577ebb1fac..fb28554b733b 100644
--- a/configs/P2020RDB-PC_36BIT_NAND_defconfig
+++ b/configs/P2020RDB-PC_36BIT_NAND_defconfig
@@ -85,6 +85,7 @@ CONFIG_LBA48=y
 CONFIG_DDR_CLK_FREQ=66666666
 CONFIG_SYS_SPD_BUS_NUM=1
 CONFIG_CHIP_SELECTS_PER_CTRL=1
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_SYS_BR0_PRELIM_BOOL=y
 CONFIG_SYS_BR0_PRELIM=0xFF800C21
 CONFIG_SYS_OR0_PRELIM=0xFFFF8396
diff --git a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig
index baeb62fa9224..48f787ec91bf 100644
--- a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig
+++ b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig
@@ -75,6 +75,7 @@ CONFIG_LBA48=y
 CONFIG_DDR_CLK_FREQ=66666666
 CONFIG_SYS_SPD_BUS_NUM=1
 CONFIG_CHIP_SELECTS_PER_CTRL=1
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_SYS_BR0_PRELIM_BOOL=y
 CONFIG_SYS_BR0_PRELIM=0xEF001001
 CONFIG_SYS_OR0_PRELIM=0xFC000FF7
diff --git a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig
index 61eb3bef5d8d..0f5af7c097d2 100644
--- a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig
+++ b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig
@@ -78,6 +78,7 @@ CONFIG_LBA48=y
 CONFIG_DDR_CLK_FREQ=66666666
 CONFIG_SYS_SPD_BUS_NUM=1
 CONFIG_CHIP_SELECTS_PER_CTRL=1
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_SYS_BR0_PRELIM_BOOL=y
 CONFIG_SYS_BR0_PRELIM=0xEF001001
 CONFIG_SYS_OR0_PRELIM=0xFC000FF7
diff --git a/configs/P2020RDB-PC_36BIT_defconfig b/configs/P2020RDB-PC_36BIT_defconfig
index 0c926455fad4..9b376595e7b8 100644
--- a/configs/P2020RDB-PC_36BIT_defconfig
+++ b/configs/P2020RDB-PC_36BIT_defconfig
@@ -54,6 +54,7 @@ CONFIG_LBA48=y
 CONFIG_DDR_CLK_FREQ=66666666
 CONFIG_SYS_SPD_BUS_NUM=1
 CONFIG_CHIP_SELECTS_PER_CTRL=1
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_SYS_BR0_PRELIM_BOOL=y
 CONFIG_SYS_BR0_PRELIM=0xEF001001
 CONFIG_SYS_OR0_PRELIM=0xFC000FF7
diff --git a/configs/P2020RDB-PC_NAND_defconfig b/configs/P2020RDB-PC_NAND_defconfig
index 08bf6daee680..6cb88863b9f4 100644
--- a/configs/P2020RDB-PC_NAND_defconfig
+++ b/configs/P2020RDB-PC_NAND_defconfig
@@ -84,6 +84,7 @@ CONFIG_LBA48=y
 CONFIG_DDR_CLK_FREQ=66666666
 CONFIG_SYS_SPD_BUS_NUM=1
 CONFIG_CHIP_SELECTS_PER_CTRL=1
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_SYS_BR0_PRELIM_BOOL=y
 CONFIG_SYS_BR0_PRELIM=0xFF800C21
 CONFIG_SYS_OR0_PRELIM=0xFFFF8396
diff --git a/configs/P2020RDB-PC_SDCARD_defconfig b/configs/P2020RDB-PC_SDCARD_defconfig
index 442ca23a7aef..cd91e8903a67 100644
--- a/configs/P2020RDB-PC_SDCARD_defconfig
+++ b/configs/P2020RDB-PC_SDCARD_defconfig
@@ -74,6 +74,7 @@ CONFIG_LBA48=y
 CONFIG_DDR_CLK_FREQ=66666666
 CONFIG_SYS_SPD_BUS_NUM=1
 CONFIG_CHIP_SELECTS_PER_CTRL=1
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_SYS_BR0_PRELIM_BOOL=y
 CONFIG_SYS_BR0_PRELIM=0xEF001001
 CONFIG_SYS_OR0_PRELIM=0xFC000FF7
diff --git a/configs/P2020RDB-PC_SPIFLASH_defconfig b/configs/P2020RDB-PC_SPIFLASH_defconfig
index a1ea8e570a2c..3f4fa81f75cd 100644
--- a/configs/P2020RDB-PC_SPIFLASH_defconfig
+++ b/configs/P2020RDB-PC_SPIFLASH_defconfig
@@ -77,6 +77,7 @@ CONFIG_LBA48=y
 CONFIG_DDR_CLK_FREQ=66666666
 CONFIG_SYS_SPD_BUS_NUM=1
 CONFIG_CHIP_SELECTS_PER_CTRL=1
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_SYS_BR0_PRELIM_BOOL=y
 CONFIG_SYS_BR0_PRELIM=0xEF001001
 CONFIG_SYS_OR0_PRELIM=0xFC000FF7
diff --git a/configs/P2020RDB-PC_defconfig b/configs/P2020RDB-PC_defconfig
index ddac11060a7a..228f36af9a95 100644
--- a/configs/P2020RDB-PC_defconfig
+++ b/configs/P2020RDB-PC_defconfig
@@ -53,6 +53,7 @@ CONFIG_LBA48=y
 CONFIG_DDR_CLK_FREQ=66666666
 CONFIG_SYS_SPD_BUS_NUM=1
 CONFIG_CHIP_SELECTS_PER_CTRL=1
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_SYS_BR0_PRELIM_BOOL=y
 CONFIG_SYS_BR0_PRELIM=0xEF001001
 CONFIG_SYS_OR0_PRELIM=0xFC000FF7
diff --git a/configs/ls1021aqds_nand_defconfig b/configs/ls1021aqds_nand_defconfig
index cfa81baff608..9ab66cd53c29 100644
--- a/configs/ls1021aqds_nand_defconfig
+++ b/configs/ls1021aqds_nand_defconfig
@@ -95,6 +95,7 @@ CONFIG_DYNAMIC_DDR_CLK_FREQ=y
 CONFIG_SYS_FSL_DDR3=y
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_MPC8XXX_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
diff --git a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig
index 0062e8a65792..e504fcb6c180 100644
--- a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig
+++ b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig
@@ -62,6 +62,7 @@ CONFIG_DYNAMIC_DDR_CLK_FREQ=y
 CONFIG_SYS_FSL_DDR3=y
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_MPC8XXX_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
diff --git a/configs/ls1021aqds_nor_defconfig b/configs/ls1021aqds_nor_defconfig
index 1434817e1c4d..42708b70f6bc 100644
--- a/configs/ls1021aqds_nor_defconfig
+++ b/configs/ls1021aqds_nor_defconfig
@@ -65,6 +65,7 @@ CONFIG_DYNAMIC_DDR_CLK_FREQ=y
 CONFIG_SYS_FSL_DDR3=y
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_MPC8XXX_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
diff --git a/configs/ls1021aqds_nor_lpuart_defconfig b/configs/ls1021aqds_nor_lpuart_defconfig
index 9bfbe2eff97d..925b376086fb 100644
--- a/configs/ls1021aqds_nor_lpuart_defconfig
+++ b/configs/ls1021aqds_nor_lpuart_defconfig
@@ -65,6 +65,7 @@ CONFIG_DYNAMIC_DDR_CLK_FREQ=y
 CONFIG_SYS_FSL_DDR3=y
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_MPC8XXX_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
diff --git a/configs/ls1021aqds_qspi_defconfig b/configs/ls1021aqds_qspi_defconfig
index 02d056f4e6c7..4e24e43c2fc6 100644
--- a/configs/ls1021aqds_qspi_defconfig
+++ b/configs/ls1021aqds_qspi_defconfig
@@ -62,6 +62,7 @@ CONFIG_FSL_CAAM=y
 CONFIG_SYS_FSL_DDR3=y
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_MPC8XXX_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
diff --git a/configs/ls1021aqds_sdcard_ifc_defconfig b/configs/ls1021aqds_sdcard_ifc_defconfig
index 164e8b017680..d5f6c5c25cff 100644
--- a/configs/ls1021aqds_sdcard_ifc_defconfig
+++ b/configs/ls1021aqds_sdcard_ifc_defconfig
@@ -93,6 +93,7 @@ CONFIG_DYNAMIC_DDR_CLK_FREQ=y
 CONFIG_SYS_FSL_DDR3=y
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_MPC8XXX_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
diff --git a/configs/ls1021aqds_sdcard_qspi_defconfig b/configs/ls1021aqds_sdcard_qspi_defconfig
index 8a6357b0b21b..addd100b2b28 100644
--- a/configs/ls1021aqds_sdcard_qspi_defconfig
+++ b/configs/ls1021aqds_sdcard_qspi_defconfig
@@ -89,6 +89,7 @@ CONFIG_FSL_CAAM=y
 CONFIG_SYS_FSL_DDR3=y
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_MPC8XXX_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
diff --git a/configs/ls1043ardb_SECURE_BOOT_defconfig b/configs/ls1043ardb_SECURE_BOOT_defconfig
index cf106de2bc05..a8328681ec8e 100644
--- a/configs/ls1043ardb_SECURE_BOOT_defconfig
+++ b/configs/ls1043ardb_SECURE_BOOT_defconfig
@@ -45,6 +45,7 @@ CONFIG_ETHPRIME="FM1 at DTSEC3"
 CONFIG_DM=y
 # CONFIG_DDR_SPD is not set
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_MPC8XXX_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
diff --git a/configs/ls1043ardb_defconfig b/configs/ls1043ardb_defconfig
index 454f3dccbba5..243a03030a98 100644
--- a/configs/ls1043ardb_defconfig
+++ b/configs/ls1043ardb_defconfig
@@ -49,6 +49,7 @@ CONFIG_DM=y
 CONFIG_FSL_CAAM=y
 # CONFIG_DDR_SPD is not set
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_MPC8XXX_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
diff --git a/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig
index 2f1676310dc2..38442c19b4ea 100644
--- a/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig
@@ -44,6 +44,7 @@ CONFIG_ETHPRIME="FM1 at DTSEC3"
 CONFIG_DM=y
 # CONFIG_DDR_SPD is not set
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_MPC8XXX_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
diff --git a/configs/ls1043ardb_tfa_defconfig b/configs/ls1043ardb_tfa_defconfig
index 5d3618319596..e065c7236656 100644
--- a/configs/ls1043ardb_tfa_defconfig
+++ b/configs/ls1043ardb_tfa_defconfig
@@ -51,6 +51,7 @@ CONFIG_DM=y
 CONFIG_FSL_CAAM=y
 # CONFIG_DDR_SPD is not set
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_SYS_DDR_RAW_TIMING=y
 CONFIG_MPC8XXX_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
diff --git a/drivers/ddr/fsl/Kconfig b/drivers/ddr/fsl/Kconfig
index 6a29b23bab7e..d93ed8d2feb6 100644
--- a/drivers/ddr/fsl/Kconfig
+++ b/drivers/ddr/fsl/Kconfig
@@ -175,6 +175,13 @@ config ECC_INIT_VIA_DDRCONTROLLER
 	  Use the DDR controller to auto initialize memory.  If not enabled,
 	  the DMA controller is responsible for doing this.
 
+config SYS_DDR_RAW_TIMING
+	bool "Get DDR timing information from something other than SPD"
+	help
+	  This is common with soldered DDR chips onboard without SPD. DDR raw
+	  timing parameters are extracted from datasheet and hard-coded into
+	  header files or board specific files.
+
 endif
 
 menu "PowerPC / M68K initial memory controller definitions (FLASH, SDRAM, etc)"
diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h
index 94fa3174de30..200b88050cc7 100644
--- a/include/configs/P1010RDB.h
+++ b/include/configs/P1010RDB.h
@@ -109,7 +109,6 @@
 #define CONFIG_L2_CACHE			/* toggle L2 cache */
 
 /* DDR Setup */
-#define CONFIG_SYS_DDR_RAW_TIMING
 #define SPD_EEPROM_ADDRESS		0x52
 
 #define CONFIG_MEM_INIT_VALUE		0xDeadBeef
diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h
index 9d68f2568df4..2ccfd87bfb05 100644
--- a/include/configs/T102xRDB.h
+++ b/include/configs/T102xRDB.h
@@ -129,7 +129,6 @@
 #define SPD_EEPROM_ADDRESS	0x51
 #define CONFIG_SYS_SDRAM_SIZE	4096	/* for fixed parameter use */
 #elif defined(CONFIG_TARGET_T1023RDB)
-#define CONFIG_SYS_DDR_RAW_TIMING
 #define CONFIG_SYS_SDRAM_SIZE   2048
 #endif
 
diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h
index dd389a9e16e8..012b47116b98 100644
--- a/include/configs/ls1021aqds.h
+++ b/include/configs/ls1021aqds.h
@@ -24,10 +24,6 @@
 
 #define SPD_EEPROM_ADDRESS		0x51
 
-#ifndef CONFIG_SYS_FSL_DDR4
-#define CONFIG_SYS_DDR_RAW_TIMING
-#endif
-
 #define CONFIG_SYS_DDR_SDRAM_BASE	0x80000000UL
 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
 
diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h
index f39a94065569..411721c12545 100644
--- a/include/configs/ls1043ardb.h
+++ b/include/configs/ls1043ardb.h
@@ -13,7 +13,6 @@
 /* Physical Memory Map */
 
 #ifndef CONFIG_SPL
-#define CONFIG_SYS_DDR_RAW_TIMING
 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 #endif
 
diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h
index f9eb829cda26..d2978713e6b7 100644
--- a/include/configs/ls2080a_common.h
+++ b/include/configs/ls2080a_common.h
@@ -16,10 +16,6 @@
 
 /* Link Definitions */
 
-#ifndef CONFIG_SYS_FSL_DDR4
-#define CONFIG_SYS_DDR_RAW_TIMING
-#endif
-
 #define CONFIG_SYS_FSL_DDR_INTLV_256B	/* force 256 byte interleaving */
 
 #define CONFIG_VERY_BIG_RAM
diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
index 1e5467807053..39552be32b3c 100644
--- a/include/configs/p1_p2_rdb_pc.h
+++ b/include/configs/p1_p2_rdb_pc.h
@@ -115,7 +115,6 @@
 #define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
 
 /* DDR Setup */
-#define CONFIG_SYS_DDR_RAW_TIMING
 #define SPD_EEPROM_ADDRESS 0x52
 
 #if defined(CONFIG_TARGET_P1020RDB_PD)
-- 
2.25.1

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