[PATCH v1 08/11] rockchip: rk3568: enable automatic clock gating

[Kever Yang]

Hi Peter,

On 2022/2/22 09:31, Peter Geis wrote:
> Enable automatic clock gating on rk3568, which solves a 7c temperature
> difference on SoQuartz compared to downstream.
>
> Signed-off-by: Peter Geis <pgwipeout at gmail.com>


Reviewed-by: Kever Yang <kever.yang at rock-chips.com>


Thanks,
- Kever
> ---
>   arch/arm/mach-rockchip/rk3568/rk3568.c | 23 +++++++++++++++++++++++
>   1 file changed, 23 insertions(+)
>
> diff --git a/arch/arm/mach-rockchip/rk3568/rk3568.c b/arch/arm/mach-rockchip/rk3568/rk3568.c
> index 5f239d89a7a9..0e0a7f5b54f2 100644
> --- a/arch/arm/mach-rockchip/rk3568/rk3568.c
> +++ b/arch/arm/mach-rockchip/rk3568/rk3568.c
> @@ -25,6 +25,15 @@
>   #define EMMC_HPROT_SECURE_CTRL		0x03
>   #define SDMMC0_HPROT_SECURE_CTRL	0x01
>   
> +#define PMU_BASE_ADDR		0xfdd90000
> +#define PMU_NOC_AUTO_CON0	(0x70)
> +#define PMU_NOC_AUTO_CON1	(0x74)
> +#define EDP_PHY_GRF_BASE	0xfdcb0000
> +#define EDP_PHY_GRF_CON0	(EDP_PHY_GRF_BASE + 0x00)
> +#define EDP_PHY_GRF_CON10	(EDP_PHY_GRF_BASE + 0x28)
> +#define CPU_GRF_BASE		0xfdc30000
> +#define GRF_CORE_PVTPLL_CON0	(0x10)
> +
>   /* PMU_GRF_GPIO0D_IOMUX_L */
>   enum {
>   	GPIO0D1_SHIFT		= 4,
> @@ -99,6 +108,20 @@ void board_debug_uart_init(void)
>   int arch_cpu_init(void)
>   {
>   #ifdef CONFIG_SPL_BUILD
> +	/*
> +	 * When perform idle operation, corresponding clock can
> +	 * be opened or gated automatically.
> +	 */
> +	writel(0xffffffff, PMU_BASE_ADDR + PMU_NOC_AUTO_CON0);
> +	writel(0x000f000f, PMU_BASE_ADDR + PMU_NOC_AUTO_CON1);
> +
> +	/* Disable eDP phy by default */
> +	writel(0x00070007, EDP_PHY_GRF_CON10);
> +	writel(0x0ff10ff1, EDP_PHY_GRF_CON0);
> +
> +	/* Set core pvtpll ring length */
> +	writel(0x00ff002b, CPU_GRF_BASE + GRF_CORE_PVTPLL_CON0);
> +
>   	/* Set the emmc sdmmc0 to secure */
>   	rk_clrreg(SGRF_BASE + SGRF_SOC_CON4, (EMMC_HPROT_SECURE_CTRL << 11
>   		| SDMMC0_HPROT_SECURE_CTRL << 4));