[PATCH] mtd: spi-nor: Parse SFDP Command Sequence to change to Octal DDR(8D-8D-8D) mode

liao jaime jaimeliao.tw at gmail.com
Wed Mar 16 03:41:40 CET 2022

Hi Tudor

> On 3/15/22 10:45, liao jaime wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> >
> > Hi
> >
> >> Hi,
> >>
> >> On 3/10/22 08:59, JaimeLiao wrote:
> >>> +static int spi_nor_generall_octal_dtr_enable(struct spi_nor *nor)
> >>
> >> Is there a disable method too? If not, can we deduce it?
> > Because of difference with flash vendors, I think it is hard to deduce the
> > method "spi_nor_generall_octal_dtr_disable".
> >>
> I've quickly skimmed through the code it seems that once octal is enabled
> and you reset the board, the flash remains in octal mode if it doesn't
> have a dedicated hardware reset line and the octal bit is non volatile.
> This is bad because there might be ROMs that don't know 8d-8d-8d mode and
> you'll break the boot sequence for them.

spi_nor_soft_reset will execute at spi_nor_scan and spi_nor_remove.
After spi_nor_soft_reset, flash will back to 1-1-1 mode.
I think we don't need disable method for backing 1-1-1 mode.


More information about the U-Boot mailing list