[PATCH v2 4/9] arm: imx: imx8mm: add enable_pwm_clk function
Tommaso Merciai
tommaso.merciai at amarulasolutions.com
Wed Mar 16 16:27:40 CET 2022
Add function enable_pwm_clk into in clock_imx8mm.c. This
function first configure, then enable pwm clock from clock control
register. The following configuration is used:
source(0) -> 24 MHz ref clock
div(0) -> no division for this clock
References:
- iMX8MMRM.pdf p 303
Signed-off-by: Tommaso Merciai <tommaso.merciai at amarulasolutions.com>
---
Changes since v1:
- Fix enable_pwm_clk function implementation. Now is generic for all pwm clks
arch/arm/mach-imx/imx8m/clock_imx8mm.c | 53 ++++++++++++++++++++++++++
1 file changed, 53 insertions(+)
diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
index 49945faf2c..ffb9456607 100644
--- a/arch/arm/mach-imx/imx8m/clock_imx8mm.c
+++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
@@ -313,6 +313,59 @@ void enable_usboh3_clk(unsigned int enable)
}
}
+void enable_pwm_clk(u32 index, unsigned char enable)
+{
+ switch (index) {
+ case 0:
+ if (enable) {
+ clock_enable(CCGR_PWM1, false);
+ clock_set_target_val(PWM1_CLK_ROOT, CLK_ROOT_ON |
+ CLK_ROOT_SOURCE_SEL(0) |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1));
+ clock_enable(CCGR_PWM1, true);
+ } else {
+ clock_enable(CCGR_PWM1, false);
+ }
+ return;
+ case 1:
+ if (enable) {
+ clock_enable(CCGR_PWM2, false);
+ clock_set_target_val(PWM2_CLK_ROOT, CLK_ROOT_ON |
+ CLK_ROOT_SOURCE_SEL(0) |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1));
+ clock_enable(CCGR_PWM2, true);
+ } else {
+ clock_enable(CCGR_PWM2, false);
+ }
+ return;
+ case 2:
+ if (enable) {
+ clock_enable(CCGR_PWM3, false);
+ clock_set_target_val(PWM3_CLK_ROOT, CLK_ROOT_ON |
+ CLK_ROOT_SOURCE_SEL(0) |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1));
+ clock_enable(CCGR_PWM3, true);
+ } else {
+ clock_enable(CCGR_PWM3, false);
+ }
+ return;
+ case 3:
+ if (enable) {
+ clock_enable(CCGR_PWM4, false);
+ clock_set_target_val(PWM4_CLK_ROOT, CLK_ROOT_ON |
+ CLK_ROOT_SOURCE_SEL(0) |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1));
+ clock_enable(CCGR_PWM4, true);
+ } else {
+ clock_enable(CCGR_PWM4, false);
+ }
+ return;
+ default:
+ printf("Invalid pwm index\n");
+ return;
+ }
+}
+
void init_uart_clk(u32 index)
{
/*
--
2.25.1
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