[EXT] [PATCH] ARM: imx: romapi: Repair FlexSPI NOR boot offset

[Marek Vasut]

On 3/21/22 04:35, Ye Li wrote:
> Hi Marek,

Hi,

>> diff --git a/arch/arm/mach-imx/spl_imx_romapi.c b/arch/arm/mach-
>> imx/spl_imx_romapi.c
>> index d827de375a6..c47f5a6bdb4 100644
>> --- a/arch/arm/mach-imx/spl_imx_romapi.c
>> +++ b/arch/arm/mach-imx/spl_imx_romapi.c
>> @@ -38,14 +38,8 @@ ulong spl_romapi_raw_seekable_read(u32 offset, u32
>> size, void *buf)
>>
>>   ulong __weak spl_romapi_get_uboot_base(u32 image_offset, u32
>> rom_bt_dev)
>>   {
>> -       u32 offset;
>> -
>> -       if (((rom_bt_dev >> 16) & 0xff) ==  BT_DEV_TYPE_FLEXSPINOR)
>> -               offset = CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR *
>> 512;
>> -       else
>> -               offset = image_offset +
>> CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512 - 0x8000;
>> -
>> -       return offset;
>> +       return image_offset +
>> +               (CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512 -
>> 0x8000);
>>   }
> 
> The change is problematic to flexspi.

Yes, I need this change to get boot from flexspi working on i.MX8MP, 
without this change writing flash.bin to flexspi results in unbootable 
system.

> Actually u-boot.itb is fixed at device offset 0x60000 (= 512 * 0x300)
> for flexspi/emmc/sd.The case is the image_offset for emmc/sd may vary according to the
> primary boot or secondary boot and the eMMC user partition or boot
> partition.
> 
> If you changed to "image_offset +
> (CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512 - 0x8000", the address
> for flexspi becomes 0x59000 (= 0x1000 + 0x60000 - 0x8000)

This is how I populate the FlexSPI on MX8MP:

dhcp ${loadaddr} 192.168.1.1:flash.bin ; \
\
setexpr sfaddr ${loadaddr} - 0x1000 ; \
\
base ${sfaddr} ; \
mw 0 0 0x400 ; \
mw 0x400 0x42464346 ; \
mw 0x404 0x56010000 ; \
mw 0x40c 00030300 ; \
mw 0x444 0x00020101 ; \
mw 0x450 0x10000000 ; \
mw 0x480 0x0818040b ; \
mw 0x484 0x24043008 ; \
mw 0x5c0 0x100 ; \
mw 0x5c4 0x10000 ; \
base 0 ; \
\
setexpr filesize ${filesize} + 0x1000 ; \
\
sf probe && sf update ${sfaddr} 0 ${filesize}