[PATCH v5 3/3] clk: imx8m: reduce rate table duplication
Adam Ford
aford173 at gmail.com
Tue Mar 22 14:49:01 CET 2022
On Tue, Mar 22, 2022 at 8:02 AM Angus Ainslie <angus at akkea.ca> wrote:
>
> Re-factor the imx8m[nmpq] rate tables into the common pll1416x clock
> driver.
>
> 43cdaa1567ad3 ("clk: imx8mm: Move 1443X/1416X PLL clock structure to common place")
>
I did a clk dump before this series and after this series then
compared the outputs to look for changes on an imx8mm. None were
identified.
Tested-by: Adam Ford <aford173 at gmail.com> #imx8mm-beacon
> Signed-off-by: Angus Ainslie <angus at akkea.ca>
> ---
> drivers/clk/imx/clk-imx8mm.c | 60 +++-----------------------------
> drivers/clk/imx/clk-imx8mn.c | 60 +++-----------------------------
> drivers/clk/imx/clk-imx8mp.c | 65 ++++++-----------------------------
> drivers/clk/imx/clk-imx8mq.c | 59 ++++---------------------------
> drivers/clk/imx/clk-pll14xx.c | 61 ++++++++++++++++++++++++++++++++
> drivers/clk/imx/clk.h | 4 +++
> 6 files changed, 91 insertions(+), 218 deletions(-)
>
> diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c
> index 443bbdae332..11213212620 100644
> --- a/drivers/clk/imx/clk-imx8mm.c
> +++ b/drivers/clk/imx/clk-imx8mm.c
> @@ -15,56 +15,6 @@
>
> #include "clk.h"
>
> -#define PLL_1416X_RATE(_rate, _m, _p, _s) \
> - { \
> - .rate = (_rate), \
> - .mdiv = (_m), \
> - .pdiv = (_p), \
> - .sdiv = (_s), \
> - }
> -
> -#define PLL_1443X_RATE(_rate, _m, _p, _s, _k) \
> - { \
> - .rate = (_rate), \
> - .mdiv = (_m), \
> - .pdiv = (_p), \
> - .sdiv = (_s), \
> - .kdiv = (_k), \
> - }
> -
> -static const struct imx_pll14xx_rate_table imx8mm_pll1416x_tbl[] = {
> - PLL_1416X_RATE(1800000000U, 225, 3, 0),
> - PLL_1416X_RATE(1600000000U, 200, 3, 0),
> - PLL_1416X_RATE(1200000000U, 300, 3, 1),
> - PLL_1416X_RATE(1000000000U, 250, 3, 1),
> - PLL_1416X_RATE(800000000U, 200, 3, 1),
> - PLL_1416X_RATE(750000000U, 250, 2, 2),
> - PLL_1416X_RATE(700000000U, 350, 3, 2),
> - PLL_1416X_RATE(600000000U, 300, 3, 2),
> -};
> -
> -static const struct imx_pll14xx_rate_table imx8mm_drampll_tbl[] = {
> - PLL_1443X_RATE(650000000U, 325, 3, 2, 0),
> -};
> -
> -static struct imx_pll14xx_clk imx8mm_dram_pll __initdata = {
> - .type = PLL_1443X,
> - .rate_table = imx8mm_drampll_tbl,
> - .rate_count = ARRAY_SIZE(imx8mm_drampll_tbl),
> -};
> -
> -static struct imx_pll14xx_clk imx8mm_arm_pll __initdata = {
> - .type = PLL_1416X,
> - .rate_table = imx8mm_pll1416x_tbl,
> - .rate_count = ARRAY_SIZE(imx8mm_pll1416x_tbl),
> -};
> -
> -static struct imx_pll14xx_clk imx8mm_sys_pll __initdata = {
> - .type = PLL_1416X,
> - .rate_table = imx8mm_pll1416x_tbl,
> - .rate_count = ARRAY_SIZE(imx8mm_pll1416x_tbl),
> -};
> -
> static const char *pll_ref_sels[] = { "clock-osc-24m", "dummy", "dummy", "dummy", };
> static const char *dram_pll_bypass_sels[] = {"dram_pll", "dram_pll_ref_sel", };
> static const char *arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", };
> @@ -164,19 +114,19 @@ static int imx8mm_clk_probe(struct udevice *dev)
>
> clk_dm(IMX8MM_DRAM_PLL,
> imx_clk_pll14xx("dram_pll", "dram_pll_ref_sel",
> - base + 0x50, &imx8mm_dram_pll));
> + base + 0x50, &imx_1443x_dram_pll));
> clk_dm(IMX8MM_ARM_PLL,
> imx_clk_pll14xx("arm_pll", "arm_pll_ref_sel",
> - base + 0x84, &imx8mm_arm_pll));
> + base + 0x84, &imx_1416x_pll));
> clk_dm(IMX8MM_SYS_PLL1,
> imx_clk_pll14xx("sys_pll1", "sys_pll1_ref_sel",
> - base + 0x94, &imx8mm_sys_pll));
> + base + 0x94, &imx_1416x_pll));
> clk_dm(IMX8MM_SYS_PLL2,
> imx_clk_pll14xx("sys_pll2", "sys_pll2_ref_sel",
> - base + 0x104, &imx8mm_sys_pll));
> + base + 0x104, &imx_1416x_pll));
> clk_dm(IMX8MM_SYS_PLL3,
> imx_clk_pll14xx("sys_pll3", "sys_pll3_ref_sel",
> - base + 0x114, &imx8mm_sys_pll));
> + base + 0x114, &imx_1416x_pll));
>
> /* PLL bypass out */
> clk_dm(IMX8MM_DRAM_PLL_BYPASS,
> diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c
> index bb62138f8ca..15d7599cfb7 100644
> --- a/drivers/clk/imx/clk-imx8mn.c
> +++ b/drivers/clk/imx/clk-imx8mn.c
> @@ -15,56 +15,6 @@
>
> #include "clk.h"
>
> -#define PLL_1416X_RATE(_rate, _m, _p, _s) \
> - { \
> - .rate = (_rate), \
> - .mdiv = (_m), \
> - .pdiv = (_p), \
> - .sdiv = (_s), \
> - }
> -
> -#define PLL_1443X_RATE(_rate, _m, _p, _s, _k) \
> - { \
> - .rate = (_rate), \
> - .mdiv = (_m), \
> - .pdiv = (_p), \
> - .sdiv = (_s), \
> - .kdiv = (_k), \
> - }
> -
> -static const struct imx_pll14xx_rate_table imx8mn_pll1416x_tbl[] = {
> - PLL_1416X_RATE(1800000000U, 225, 3, 0),
> - PLL_1416X_RATE(1600000000U, 200, 3, 0),
> - PLL_1416X_RATE(1200000000U, 300, 3, 1),
> - PLL_1416X_RATE(1000000000U, 250, 3, 1),
> - PLL_1416X_RATE(800000000U, 200, 3, 1),
> - PLL_1416X_RATE(750000000U, 250, 2, 2),
> - PLL_1416X_RATE(700000000U, 350, 3, 2),
> - PLL_1416X_RATE(600000000U, 300, 3, 2),
> -};
> -
> -static const struct imx_pll14xx_rate_table imx8mn_drampll_tbl[] = {
> - PLL_1443X_RATE(650000000U, 325, 3, 2, 0),
> -};
> -
> -static struct imx_pll14xx_clk imx8mn_dram_pll __initdata = {
> - .type = PLL_1443X,
> - .rate_table = imx8mn_drampll_tbl,
> - .rate_count = ARRAY_SIZE(imx8mn_drampll_tbl),
> -};
> -
> -static struct imx_pll14xx_clk imx8mn_arm_pll __initdata = {
> - .type = PLL_1416X,
> - .rate_table = imx8mn_pll1416x_tbl,
> - .rate_count = ARRAY_SIZE(imx8mn_pll1416x_tbl),
> -};
> -
> -static struct imx_pll14xx_clk imx8mn_sys_pll __initdata = {
> - .type = PLL_1416X,
> - .rate_table = imx8mn_pll1416x_tbl,
> - .rate_count = ARRAY_SIZE(imx8mn_pll1416x_tbl),
> -};
> -
> static const char *pll_ref_sels[] = { "clock-osc-24m", "dummy", "dummy", "dummy", };
> static const char *dram_pll_bypass_sels[] = {"dram_pll", "dram_pll_ref_sel", };
> static const char *arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", };
> @@ -172,19 +122,19 @@ static int imx8mn_clk_probe(struct udevice *dev)
>
> clk_dm(IMX8MN_DRAM_PLL,
> imx_clk_pll14xx("dram_pll", "dram_pll_ref_sel",
> - base + 0x50, &imx8mn_dram_pll));
> + base + 0x50, &imx_1443x_dram_pll));
> clk_dm(IMX8MN_ARM_PLL,
> imx_clk_pll14xx("arm_pll", "arm_pll_ref_sel",
> - base + 0x84, &imx8mn_arm_pll));
> + base + 0x84, &imx_1416x_pll));
> clk_dm(IMX8MN_SYS_PLL1,
> imx_clk_pll14xx("sys_pll1", "sys_pll1_ref_sel",
> - base + 0x94, &imx8mn_sys_pll));
> + base + 0x94, &imx_1416x_pll));
> clk_dm(IMX8MN_SYS_PLL2,
> imx_clk_pll14xx("sys_pll2", "sys_pll2_ref_sel",
> - base + 0x104, &imx8mn_sys_pll));
> + base + 0x104, &imx_1416x_pll));
> clk_dm(IMX8MN_SYS_PLL3,
> imx_clk_pll14xx("sys_pll3", "sys_pll3_ref_sel",
> - base + 0x114, &imx8mn_sys_pll));
> + base + 0x114, &imx_1416x_pll));
>
> /* PLL bypass out */
> clk_dm(IMX8MN_DRAM_PLL_BYPASS,
> diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c
> index ad84ce38ede..31689e02927 100644
> --- a/drivers/clk/imx/clk-imx8mp.c
> +++ b/drivers/clk/imx/clk-imx8mp.c
> @@ -15,56 +15,6 @@
>
> #include "clk.h"
>
> -#define PLL_1416X_RATE(_rate, _m, _p, _s) \
> - { \
> - .rate = (_rate), \
> - .mdiv = (_m), \
> - .pdiv = (_p), \
> - .sdiv = (_s), \
> - }
> -
> -#define PLL_1443X_RATE(_rate, _m, _p, _s, _k) \
> - { \
> - .rate = (_rate), \
> - .mdiv = (_m), \
> - .pdiv = (_p), \
> - .sdiv = (_s), \
> - .kdiv = (_k), \
> - }
> -
> -static const struct imx_pll14xx_rate_table imx8mp_pll1416x_tbl[] = {
> - PLL_1416X_RATE(1800000000U, 225, 3, 0),
> - PLL_1416X_RATE(1600000000U, 200, 3, 0),
> - PLL_1416X_RATE(1200000000U, 300, 3, 1),
> - PLL_1416X_RATE(1000000000U, 250, 3, 1),
> - PLL_1416X_RATE(800000000U, 200, 3, 1),
> - PLL_1416X_RATE(750000000U, 250, 2, 2),
> - PLL_1416X_RATE(700000000U, 350, 3, 2),
> - PLL_1416X_RATE(600000000U, 300, 3, 2),
> -};
> -
> -static const struct imx_pll14xx_rate_table imx8mp_drampll_tbl[] = {
> - PLL_1443X_RATE(650000000U, 325, 3, 2, 0),
> -};
> -
> -static struct imx_pll14xx_clk imx8mp_dram_pll __initdata = {
> - .type = PLL_1443X,
> - .rate_table = imx8mp_drampll_tbl,
> - .rate_count = ARRAY_SIZE(imx8mp_drampll_tbl),
> -};
> -
> -static struct imx_pll14xx_clk imx8mp_arm_pll __initdata = {
> - .type = PLL_1416X,
> - .rate_table = imx8mp_pll1416x_tbl,
> - .rate_count = ARRAY_SIZE(imx8mp_pll1416x_tbl),
> -};
> -
> -static struct imx_pll14xx_clk imx8mp_sys_pll __initdata = {
> - .type = PLL_1416X,
> - .rate_table = imx8mp_pll1416x_tbl,
> - .rate_count = ARRAY_SIZE(imx8mp_pll1416x_tbl),
> -};
> -
> static const char *pll_ref_sels[] = { "clock-osc-24m", "dummy", "dummy", "dummy", };
> static const char *dram_pll_bypass_sels[] = {"dram_pll", "dram_pll_ref_sel", };
> static const char *arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", };
> @@ -198,11 +148,16 @@ static int imx8mp_clk_probe(struct udevice *dev)
> clk_dm(IMX8MP_SYS_PLL2_REF_SEL, imx_clk_mux("sys_pll2_ref_sel", base + 0x104, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
> clk_dm(IMX8MP_SYS_PLL3_REF_SEL, imx_clk_mux("sys_pll3_ref_sel", base + 0x114, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
>
> - clk_dm(IMX8MP_DRAM_PLL, imx_clk_pll14xx("dram_pll", "dram_pll_ref_sel", base + 0x50, &imx8mp_dram_pll));
> - clk_dm(IMX8MP_ARM_PLL, imx_clk_pll14xx("arm_pll", "arm_pll_ref_sel", base + 0x84, &imx8mp_arm_pll));
> - clk_dm(IMX8MP_SYS_PLL1, imx_clk_pll14xx("sys_pll1", "sys_pll1_ref_sel", base + 0x94, &imx8mp_sys_pll));
> - clk_dm(IMX8MP_SYS_PLL2, imx_clk_pll14xx("sys_pll2", "sys_pll2_ref_sel", base + 0x104, &imx8mp_sys_pll));
> - clk_dm(IMX8MP_SYS_PLL3, imx_clk_pll14xx("sys_pll3", "sys_pll3_ref_sel", base + 0x114, &imx8mp_sys_pll));
> + clk_dm(IMX8MP_DRAM_PLL, imx_clk_pll14xx("dram_pll", "dram_pll_ref_sel", base + 0x50,
> + &imx_1443x_dram_pll));
> + clk_dm(IMX8MP_ARM_PLL, imx_clk_pll14xx("arm_pll", "arm_pll_ref_sel", base + 0x84,
> + &imx_1416x_pll));
> + clk_dm(IMX8MP_SYS_PLL1, imx_clk_pll14xx("sys_pll1", "sys_pll1_ref_sel", base + 0x94,
> + &imx_1416x_pll));
> + clk_dm(IMX8MP_SYS_PLL2, imx_clk_pll14xx("sys_pll2", "sys_pll2_ref_sel", base + 0x104,
> + &imx_1416x_pll));
> + clk_dm(IMX8MP_SYS_PLL3, imx_clk_pll14xx("sys_pll3", "sys_pll3_ref_sel", base + 0x114,
> + &imx_1416x_pll));
>
> clk_dm(IMX8MP_DRAM_PLL_BYPASS, imx_clk_mux_flags("dram_pll_bypass", base + 0x50, 4, 1, dram_pll_bypass_sels, ARRAY_SIZE(dram_pll_bypass_sels), CLK_SET_RATE_PARENT));
> clk_dm(IMX8MP_ARM_PLL_BYPASS, imx_clk_mux_flags("arm_pll_bypass", base + 0x84, 4, 1, arm_pll_bypass_sels, ARRAY_SIZE(arm_pll_bypass_sels), CLK_SET_RATE_PARENT));
> diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c
> index 2a861c3edb9..a86a1b2f2d8 100644
> --- a/drivers/clk/imx/clk-imx8mq.c
> +++ b/drivers/clk/imx/clk-imx8mq.c
> @@ -16,53 +16,6 @@
>
> #include "clk.h"
>
> -#define PLL_1416X_RATE(_rate, _m, _p, _s) \
> - { \
> - .rate = (_rate), \
> - .mdiv = (_m), \
> - .pdiv = (_p), \
> - .sdiv = (_s), \
> - }
> -
> -#define PLL_1443X_RATE(_rate, _m, _p, _s, _k) \
> - { \
> - .rate = (_rate), \
> - .mdiv = (_m), \
> - .pdiv = (_p), \
> - .sdiv = (_s), \
> - .kdiv = (_k), \
> - }
> -
> -static const struct imx_pll14xx_rate_table imx8mq_pll1416x_tbl[] = {
> - PLL_1416X_RATE(1800000000U, 225, 3, 0),
> - PLL_1416X_RATE(1600000000U, 200, 3, 0),
> - PLL_1416X_RATE(1200000000U, 300, 3, 1),
> - PLL_1416X_RATE(1000000000U, 250, 3, 1),
> - PLL_1416X_RATE(800000000U, 200, 3, 1),
> - PLL_1416X_RATE(750000000U, 250, 2, 2),
> - PLL_1416X_RATE(700000000U, 350, 3, 2),
> - PLL_1416X_RATE(600000000U, 300, 3, 2),
> -};
> -
> -const struct imx_pll14xx_rate_table imx8mq_pll1443x_tbl[] = {
> - PLL_1443X_RATE(650000000U, 325, 3, 2, 0),
> - PLL_1443X_RATE(594000000U, 198, 2, 2, 0),
> - PLL_1443X_RATE(393216000U, 262, 2, 3, 9437),
> - PLL_1443X_RATE(361267200U, 361, 3, 3, 17511),
> -};
> -
> -static struct imx_pll14xx_clk imx8mq_1416x_pll __initdata = {
> - .type = PLL_1416X,
> - .rate_table = imx8mq_pll1416x_tbl,
> - .rate_count = ARRAY_SIZE(imx8mq_pll1416x_tbl),
> -};
> -
> -static struct imx_pll14xx_clk imx8mq_1443x_pll __initdata = {
> - .type = PLL_1443X,
> - .rate_table = imx8mq_pll1443x_tbl,
> - .rate_count = ARRAY_SIZE(imx8mq_pll1443x_tbl),
> -};
> -
> static const char *const pll_ref_sels[] = { "clock-osc-25m", "clock-osc-27m", "clock-phy-27m", "dummy", };
> static const char *const arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", };
> static const char *const gpu_pll_bypass_sels[] = {"gpu_pll", "gpu_pll_ref_sel", };
> @@ -199,13 +152,13 @@ static int imx8mq_clk_probe(struct udevice *dev)
>
> clk_dm(IMX8MQ_ARM_PLL,
> imx_clk_pll14xx("arm_pll", "arm_pll_ref_sel",
> - base + 0x28, &imx8mq_1416x_pll));
> + base + 0x28, &imx_1416x_pll));
> clk_dm(IMX8MQ_GPU_PLL,
> imx_clk_pll14xx("gpu_pll", "gpu_pll_ref_sel",
> - base + 0x18, &imx8mq_1416x_pll));
> + base + 0x18, &imx_1416x_pll));
> clk_dm(IMX8MQ_VPU_PLL,
> imx_clk_pll14xx("vpu_pll", "vpu_pll_ref_sel",
> - base + 0x20, &imx8mq_1416x_pll));
> + base + 0x20, &imx_1416x_pll));
>
> clk_dm(IMX8MQ_SYS1_PLL1,
> clk_register_fixed_rate(NULL, "sys1_pll", 800000000));
> @@ -215,13 +168,13 @@ static int imx8mq_clk_probe(struct udevice *dev)
> clk_register_fixed_rate(NULL, "sys3_pll", 1000000000));
> clk_dm(IMX8MQ_AUDIO_PLL1,
> imx_clk_pll14xx("audio_pll1", "audio_pll1_ref_sel",
> - base + 0x0, &imx8mq_1443x_pll));
> + base + 0x0, &imx_1443x_pll));
> clk_dm(IMX8MQ_AUDIO_PLL2,
> imx_clk_pll14xx("audio_pll2", "audio_pll2_ref_sel",
> - base + 0x8, &imx8mq_1443x_pll));
> + base + 0x8, &imx_1443x_pll));
> clk_dm(IMX8MQ_VIDEO_PLL1,
> imx_clk_pll14xx("video_pll1", "video_pll1_ref_sel",
> - base + 0x10, &imx8mq_1443x_pll));
> + base + 0x10, &imx_1443x_pll));
>
> /* PLL bypass out */
> clk_dm(IMX8MQ_ARM_PLL_BYPASS,
> diff --git a/drivers/clk/imx/clk-pll14xx.c b/drivers/clk/imx/clk-pll14xx.c
> index b0ccb6c8eda..b93c0bc64e7 100644
> --- a/drivers/clk/imx/clk-pll14xx.c
> +++ b/drivers/clk/imx/clk-pll14xx.c
> @@ -52,6 +52,67 @@ struct clk_pll14xx {
>
> #define to_clk_pll14xx(_clk) container_of(_clk, struct clk_pll14xx, clk)
>
> +#define PLL_1416X_RATE(_rate, _m, _p, _s) \
> + { \
> + .rate = (_rate), \
> + .mdiv = (_m), \
> + .pdiv = (_p), \
> + .sdiv = (_s), \
> + }
> +
> +#define PLL_1443X_RATE(_rate, _m, _p, _s, _k) \
> + { \
> + .rate = (_rate), \
> + .mdiv = (_m), \
> + .pdiv = (_p), \
> + .sdiv = (_s), \
> + .kdiv = (_k), \
> + }
> +
> +static const struct imx_pll14xx_rate_table imx_pll1416x_tbl[] = {
> + PLL_1416X_RATE(1800000000U, 225, 3, 0),
> + PLL_1416X_RATE(1600000000U, 200, 3, 0),
> + PLL_1416X_RATE(1500000000U, 375, 3, 1),
> + PLL_1416X_RATE(1400000000U, 350, 3, 1),
> + PLL_1416X_RATE(1200000000U, 300, 3, 1),
> + PLL_1416X_RATE(1000000000U, 250, 3, 1),
> + PLL_1416X_RATE(800000000U, 200, 3, 1),
> + PLL_1416X_RATE(750000000U, 250, 2, 2),
> + PLL_1416X_RATE(700000000U, 350, 3, 2),
> + PLL_1416X_RATE(600000000U, 300, 3, 2),
> +};
> +
> +const struct imx_pll14xx_rate_table imx_pll1443x_tbl[] = {
> + PLL_1443X_RATE(1039500000U, 173, 2, 1, 16384),
> + PLL_1443X_RATE(650000000U, 325, 3, 2, 0),
> + PLL_1443X_RATE(594000000U, 198, 2, 2, 0),
> + PLL_1443X_RATE(519750000U, 173, 2, 2, 16384),
> + PLL_1443X_RATE(393216000U, 262, 2, 3, 9437),
> + PLL_1443X_RATE(361267200U, 361, 3, 3, 17511),
> +};
> +
> +struct imx_pll14xx_clk imx_1443x_pll __initdata = {
> + .type = PLL_1443X,
> + .rate_table = imx_pll1443x_tbl,
> + .rate_count = ARRAY_SIZE(imx_pll1443x_tbl),
> +};
> +EXPORT_SYMBOL_GPL(imx_1443x_pll);
> +
> +struct imx_pll14xx_clk imx_1443x_dram_pll __initdata = {
> + .type = PLL_1443X,
> + .rate_table = imx_pll1443x_tbl,
> + .rate_count = ARRAY_SIZE(imx_pll1443x_tbl),
> + .flags = CLK_GET_RATE_NOCACHE,
> +};
> +EXPORT_SYMBOL_GPL(imx_1443x_dram_pll);
> +
> +struct imx_pll14xx_clk imx_1416x_pll __initdata = {
> + .type = PLL_1416X,
> + .rate_table = imx_pll1416x_tbl,
> + .rate_count = ARRAY_SIZE(imx_pll1416x_tbl),
> +};
> +EXPORT_SYMBOL_GPL(imx_1416x_pll);
> +
> static const struct imx_pll14xx_rate_table *imx_get_pll_settings(
> struct clk_pll14xx *pll, unsigned long rate)
> {
> diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h
> index 60f287046b9..0e1eaf03d41 100644
> --- a/drivers/clk/imx/clk.h
> +++ b/drivers/clk/imx/clk.h
> @@ -41,6 +41,10 @@ struct imx_pll14xx_clk {
> int flags;
> };
>
> +extern struct imx_pll14xx_clk imx_1416x_pll;
> +extern struct imx_pll14xx_clk imx_1443x_pll;
> +extern struct imx_pll14xx_clk imx_1443x_dram_pll;
> +
> struct clk *imx_clk_pll14xx(const char *name, const char *parent_name,
> void __iomem *base,
> const struct imx_pll14xx_clk *pll_clk);
> --
> 2.25.1
>
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