[PATCH] mmc: fsl_esdhc: Fix 'Internal clock never stabilised.' error

[Pali Rohár]

On Friday 06 May 2022 18:32:18 Jaehoon Chung wrote:
> On 4/30/22 03:27, Pali Rohár wrote:
> > Only newer eSDHC controllers set PRSSTAT_SDSTB flag. So do not wait until
> > flag PRSSTAT_SDSTB is set on old pre-2.2 controllers. Instead sleep for
> > fixed amount of time like it was before commit 6f883e501b65 ("mmc:
> > fsl_esdhc: Add emmc hs200 support").
> > 
> > This change fixes error 'Internal clock never stabilised.' which is printed
> > on P2020 board at every access to SD card.
> > 
> > Fixes: 6f883e501b65 ("mmc: fsl_esdhc: Add emmc hs200 support")
> > Signed-off-by: Pali Rohár <pali at kernel.org>
> 
> Reviewed-by: Jaehoon Chung <jh80.chung at samsung.com>
> 
> Just add minor question. 
> 
> > ---
> >  drivers/mmc/fsl_esdhc.c | 17 +++++++++++++++++
> >  1 file changed, 17 insertions(+)
> > 
> > diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
> > index fdf2cc290e06..3b3587bd8d72 100644
> > --- a/drivers/mmc/fsl_esdhc.c
> > +++ b/drivers/mmc/fsl_esdhc.c
> > @@ -503,6 +503,7 @@ static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock)
> >  	u32 time_out;
> >  	u32 value;
> >  	uint clk;
> > +	u32 hostver;
> >  
> >  	if (clock < mmc->cfg->f_min)
> >  		clock = mmc->cfg->f_min;
> > @@ -543,6 +544,14 @@ static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock)
> >  
> >  	esdhc_clrsetbits32(&regs->sysctl, SYSCTL_CLOCK_MASK, clk);
> >  
> > +	/* Only newer eSDHC controllers set PRSSTAT_SDSTB flag */
> > +	hostver = esdhc_read32(&priv->esdhc_regs->hostver);
> > +	if (HOSTVER_VENDOR(hostver) <= VENDOR_V_22) {
> > +		udelay(10000);
> 
> Is there any reason to use 10000?

Hello! I really do not know. This value was there before commit
6f883e501b65. This is probably question for Freescale/NXP people.

> Best Regards,
> Jaehoon Chung
> 
> > +		esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
> > +		return;
> > +	}
> > +
> >  	time_out = 20;
> >  	value = PRSSTAT_SDSTB;
> >  	while (!(esdhc_read32(&regs->prsstat) & value)) {
> > @@ -562,6 +571,7 @@ static void esdhc_clock_control(struct fsl_esdhc_priv *priv, bool enable)
> >  	struct fsl_esdhc *regs = priv->esdhc_regs;
> >  	u32 value;
> >  	u32 time_out;
> > +	u32 hostver;
> >  
> >  	value = esdhc_read32(&regs->sysctl);
> >  
> > @@ -572,6 +582,13 @@ static void esdhc_clock_control(struct fsl_esdhc_priv *priv, bool enable)
> >  
> >  	esdhc_write32(&regs->sysctl, value);
> >  
> > +	/* Only newer eSDHC controllers set PRSSTAT_SDSTB flag */
> > +	hostver = esdhc_read32(&priv->esdhc_regs->hostver);
> > +	if (HOSTVER_VENDOR(hostver) <= VENDOR_V_22) {
> > +		udelay(10000);
> > +		return;
> > +	}
> > +
> >  	time_out = 20;
> >  	value = PRSSTAT_SDSTB;
> >  	while (!(esdhc_read32(&regs->prsstat) & value)) {
>