[PATCH 4/4] spi: synquacer: simplify tx completion checking

[Jassi Brar]

On Tue, 17 May 2022 at 03:41, Masahisa Kojima
<masahisa.kojima at linaro.org> wrote:
>
> There is a TX-FIFO and Shift Register empty(TFES) status
> bit in spi controller. This commit checks the TFES bit
> to wait the TX transfer completes.
>
> Signed-off-by: Masahisa Kojima <masahisa.kojima at linaro.org>
> Signed-off-by: Satoru Okamoto <okamoto.satoru at socionext.com>
> ---
Acked-by: Jassi Brar <jaswinder.singh at linaro.org>