[PATCH V4 2/8] arm: dts: imx8m: update binman ddr firmware node name
Alper Nebi Yasak
alpernebiyasak at gmail.com
Mon May 23 23:11:46 CEST 2022
On 23/05/2022 10:01, Peng Fan (OSS) wrote:
>> Subject: Re: [PATCH V4 2/8] arm: dts: imx8m: update binman ddr firmware
>> node name
>>
>> On 20/05/2022 17:10, Peng Fan (OSS) wrote:
>>> From: Peng Fan <peng.fan at nxp.com>
>>>
>>> We are migrating to use BINMAN SYMBOLS, the current name is not a
>>> valid binman type, so update to use blob-ext@[1,2,3,4].
>>>
>>> Tested-by: Tim Harvey <tharvey at gateworks.com> #imx8m[m,n,p]-venice
>>> Signed-off-by: Peng Fan <peng.fan at nxp.com>
>>> ---
>>> arch/arm/dts/imx8mm-u-boot.dtsi | 8 ++++----
>>> arch/arm/dts/imx8mn-bsh-smm-s2-u-boot-common.dtsi | 4 ++--
>>> arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi | 8 ++++----
>>> arch/arm/dts/imx8mn-venice-u-boot.dtsi | 8 ++++----
>>> arch/arm/dts/imx8mq-u-boot.dtsi | 8 ++++----
>>> 5 files changed, 18 insertions(+), 18 deletions(-)
>>
>> I think descriptive entry names are better in general, so I prefer the old names
>> to a bunch of 'blob-ext's. Symbol resolution is done using the entry names
>> anyway, I don't see why this change would be necessary.
>
> Binman understand blob-ext, it not understand 1d-imem. If keep id-imem, or else,
> need to add several new binman types which I would not prefer.
It would work as long as you set `type = "blob-ext";` in the entry block.
Please test this diff on top of your series:
diff --git a/arch/arm/dts/imx8mm-u-boot.dtsi b/arch/arm/dts/imx8mm-u-boot.dtsi
index 19a2da30f512..8c48678625d9 100644
--- a/arch/arm/dts/imx8mm-u-boot.dtsi
+++ b/arch/arm/dts/imx8mm-u-boot.dtsi
@@ -39,25 +39,25 @@
filename = "u-boot-spl.bin";
};
- imem_1d: blob-ext at 1 {
+ ddr-1d-imem-fw {
filename = "lpddr4_pmu_train_1d_imem.bin";
align-end = <4>;
type = "blob-ext";
};
- dmem_1d: blob-ext at 2 {
+ ddr-1d-dmem-fw {
filename = "lpddr4_pmu_train_1d_dmem.bin";
align-end = <4>;
type = "blob-ext";
};
- imem_2d: blob-ext at 3 {
+ ddr-2d-imem-fw {
filename = "lpddr4_pmu_train_2d_imem.bin";
align-end = <4>;
type = "blob-ext";
};
- dmem_2d: blob-ext at 4 {
+ ddr-2d-dmem-fw {
filename = "lpddr4_pmu_train_2d_dmem.bin";
align-end = <4>;
type = "blob-ext";
diff --git a/arch/arm/dts/imx8mn-beacon-kit-u-boot.dtsi b/arch/arm/dts/imx8mn-beacon-kit-u-boot.dtsi
index 0f89c8f677fa..dc7afc05e8f9 100644
--- a/arch/arm/dts/imx8mn-beacon-kit-u-boot.dtsi
+++ b/arch/arm/dts/imx8mn-beacon-kit-u-boot.dtsi
@@ -143,24 +143,28 @@
align-end = <4>;
};
- blob_1: blob-ext at 1 {
+ ddr-1d-imem-fw {
filename = "lpddr4_pmu_train_1d_imem.bin";
align-end = <4>;
+ type = "blob-ext";
};
- blob_2: blob-ext at 2 {
+ ddr-1d-dmem-fw {
filename = "lpddr4_pmu_train_1d_dmem.bin";
align-end = <4>;
+ type = "blob-ext";
};
- blob_3: blob-ext at 3 {
+ ddr-2d-imem-fw {
filename = "lpddr4_pmu_train_2d_imem.bin";
align-end = <4>;
+ type = "blob-ext";
};
- blob_4: blob-ext at 4 {
+ ddr-2d-dmem-fw {
filename = "lpddr4_pmu_train_2d_dmem.bin";
align-end = <4>;
+ type = "blob-ext";
};
};
diff --git a/arch/arm/dts/imx8mn-bsh-smm-s2-u-boot-common.dtsi b/arch/arm/dts/imx8mn-bsh-smm-s2-u-boot-common.dtsi
index 5a52b73d7e9c..dc4cec250efa 100644
--- a/arch/arm/dts/imx8mn-bsh-smm-s2-u-boot-common.dtsi
+++ b/arch/arm/dts/imx8mn-bsh-smm-s2-u-boot-common.dtsi
@@ -111,13 +111,13 @@
filename = "u-boot-spl.bin";
};
- imem_1d: blob-ext at 1 {
+ ddr-1d-imem-fw {
filename = "ddr3_imem_1d.bin";
size = <0x8000>;
type = "blob-ext";
};
- dmem_1d: blob-ext at 2 {
+ ddr-1d-dmem-fw {
filename = "ddr3_dmem_1d.bin";
size = <0x4000>;
type = "blob-ext";
diff --git a/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi b/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
index 6f3d5cfe3c18..3f02b4aac135 100644
--- a/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
+++ b/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
@@ -151,24 +151,28 @@
align-end = <4>;
};
- blob_1: blob-ext at 1 {
+ ddr-1d-imem-fw {
filename = "ddr4_imem_1d_201810.bin";
align-end = <4>;
+ type = "blob-ext";
};
- blob_2: blob-ext at 2 {
+ ddr-1d-dmem-fw {
filename = "ddr4_dmem_1d_201810.bin";
align-end = <4>;
+ type = "blob-ext";
};
- blob_3: blob-ext at 3 {
+ ddr-2d-imem-fw {
filename = "ddr4_imem_2d_201810.bin";
align-end = <4>;
+ type = "blob-ext";
};
- blob_4: blob-ext at 4 {
+ ddr-2d-dmem-fw {
filename = "ddr4_dmem_2d_201810.bin";
align-end = <4>;
+ type = "blob-ext";
};
};
diff --git a/arch/arm/dts/imx8mn-evk-u-boot.dtsi b/arch/arm/dts/imx8mn-evk-u-boot.dtsi
index 4f6dcf307b28..4d55905736d0 100644
--- a/arch/arm/dts/imx8mn-evk-u-boot.dtsi
+++ b/arch/arm/dts/imx8mn-evk-u-boot.dtsi
@@ -36,24 +36,28 @@
align-end = <4>;
};
- blob_1: blob-ext at 1 {
+ ddr-1d-imem-fw {
filename = "lpddr4_pmu_train_1d_imem.bin";
align-end = <4>;
+ type = "blob-ext";
};
- blob_2: blob-ext at 2 {
+ ddr-1d-dmem-fw {
filename = "lpddr4_pmu_train_1d_dmem.bin";
align-end = <4>;
+ type = "blob-ext";
};
- blob_3: blob-ext at 3 {
+ ddr-2d-imem-fw {
filename = "lpddr4_pmu_train_2d_imem.bin";
align-end = <4>;
+ type = "blob-ext";
};
- blob_4: blob-ext at 4 {
+ ddr-2d-dmem-fw {
filename = "lpddr4_pmu_train_2d_dmem.bin";
align-end = <4>;
+ type = "blob-ext";
};
};
diff --git a/arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi b/arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi
index 32ef79292886..ed1ab10ded37 100644
--- a/arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi
+++ b/arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi
@@ -130,25 +130,25 @@
filename = "u-boot-spl.bin";
};
- blob_1: blob-ext at 1 {
+ ddr-1d-imem-fw {
filename = "ddr4_imem_1d.bin";
align-end = <4>;
type = "blob-ext";
};
- blob_2: blob-ext at 2 {
+ ddr-1d-dmem-fw {
filename = "ddr4_dmem_1d.bin";
align-end = <4>;
type = "blob-ext";
};
- blob_3: blob-ext at 3 {
+ ddr-2d-imem-fw {
filename = "ddr4_imem_2d.bin";
align-end = <4>;
type = "blob-ext";
};
- blob_4: blob-ext at 4 {
+ ddr-2d-dmem-fw {
filename = "ddr4_dmem_2d.bin";
align-end = <4>;
type = "blob-ext";
diff --git a/arch/arm/dts/imx8mn-venice-u-boot.dtsi b/arch/arm/dts/imx8mn-venice-u-boot.dtsi
index 03a9eb8516f9..6d6535fdbfeb 100644
--- a/arch/arm/dts/imx8mn-venice-u-boot.dtsi
+++ b/arch/arm/dts/imx8mn-venice-u-boot.dtsi
@@ -122,25 +122,25 @@
filename = "u-boot-spl.bin";
};
- imem_1d: blob-ext at 1 {
+ ddr-1d-imem-fw {
filename = "lpddr4_pmu_train_1d_imem.bin";
align-end = <4>;
type = "blob-ext";
};
- dmem_1d: blob-ext at 2 {
+ ddr-1d-dmem-fw {
filename = "lpddr4_pmu_train_1d_dmem.bin";
align-end = <4>;
type = "blob-ext";
};
- imem_2d: blob-ext at 3 {
+ ddr-2d-imem-fw {
filename = "lpddr4_pmu_train_2d_imem.bin";
align-end = <4>;
type = "blob-ext";
};
- dmem_2d: blob-ext at 4 {
+ ddr-2d-dmem-fw {
filename = "lpddr4_pmu_train_2d_dmem.bin";
align-end = <4>;
type = "blob-ext";
diff --git a/arch/arm/dts/imx8mp-u-boot.dtsi b/arch/arm/dts/imx8mp-u-boot.dtsi
index 274515a010ee..6fd4de2c9615 100644
--- a/arch/arm/dts/imx8mp-u-boot.dtsi
+++ b/arch/arm/dts/imx8mp-u-boot.dtsi
@@ -61,24 +61,28 @@
align-end = <4>;
};
- blob_1: blob-ext at 1 {
+ ddr-1d-imem-fw {
filename = "lpddr4_pmu_train_1d_imem_202006.bin";
align-end = <4>;
+ type = "blob-ext";
};
- blob_2: blob-ext at 2 {
+ ddr-1d-dmem-fw {
filename = "lpddr4_pmu_train_1d_dmem_202006.bin";
align-end = <4>;
+ type = "blob-ext";
};
- blob_3: blob-ext at 3 {
+ ddr-2d-imem-fw {
filename = "lpddr4_pmu_train_2d_imem_202006.bin";
align-end = <4>;
+ type = "blob-ext";
};
- blob_4: blob-ext at 4 {
+ ddr-2d-dmem-fw {
filename = "lpddr4_pmu_train_2d_dmem_202006.bin";
align-end = <4>;
+ type = "blob-ext";
};
};
diff --git a/arch/arm/dts/imx8mq-cm-u-boot.dtsi b/arch/arm/dts/imx8mq-cm-u-boot.dtsi
index 1b66e76ee1dc..81063083bd40 100644
--- a/arch/arm/dts/imx8mq-cm-u-boot.dtsi
+++ b/arch/arm/dts/imx8mq-cm-u-boot.dtsi
@@ -20,24 +20,28 @@
align-end = <4>;
};
- blob_1: blob-ext at 1 {
+ ddr-1d-imem-fw {
filename = "lpddr4_pmu_train_1d_imem.bin";
align-end = <4>;
+ type = "blob-ext";
};
- blob_2: blob-ext at 2 {
+ ddr-1d-dmem-fw {
filename = "lpddr4_pmu_train_1d_dmem.bin";
align-end = <4>;
+ type = "blob-ext";
};
- blob_3: blob-ext at 3 {
+ ddr-2d-imem-fw {
filename = "lpddr4_pmu_train_2d_imem.bin";
align-end = <4>;
+ type = "blob-ext";
};
- blob_4: blob-ext at 4 {
+ ddr-2d-dmem-fw {
filename = "lpddr4_pmu_train_2d_dmem.bin";
align-end = <4>;
+ type = "blob-ext";
};
};
diff --git a/arch/arm/dts/imx8mq-u-boot.dtsi b/arch/arm/dts/imx8mq-u-boot.dtsi
index e683e9184725..000ee545ee7f 100644
--- a/arch/arm/dts/imx8mq-u-boot.dtsi
+++ b/arch/arm/dts/imx8mq-u-boot.dtsi
@@ -22,25 +22,25 @@
filename = "u-boot-spl.bin";
};
- imem_1d: blob-ext at 1 {
+ ddr-1d-imem-fw {
filename = "lpddr4_pmu_train_1d_imem.bin";
align-end = <4>;
type = "blob-ext";
};
- dmem_1d: blob-ext at 2 {
+ ddr-1d-dmem-fw {
filename = "lpddr4_pmu_train_1d_dmem.bin";
align-end = <4>;
type = "blob-ext";
};
- imem_2d: blob-ext at 3 {
+ ddr-2d-imem-fw {
filename = "lpddr4_pmu_train_2d_imem.bin";
align-end = <4>;
type = "blob-ext";
};
- dmem_2d: blob-ext at 4 {
+ ddr-2d-dmem-fw {
filename = "lpddr4_pmu_train_2d_dmem.bin";
align-end = <4>;
type = "blob-ext";
diff --git a/drivers/ddr/imx/imx8m/helper.c b/drivers/ddr/imx/imx8m/helper.c
index b3bd57531b76..3764cffabc90 100644
--- a/drivers/ddr/imx/imx8m/helper.c
+++ b/drivers/ddr/imx/imx8m/helper.c
@@ -26,18 +26,18 @@ DECLARE_GLOBAL_DATA_PTR;
#define DMEM_OFFSET_ADDR 0x00054000
#define DDR_TRAIN_CODE_BASE_ADDR IP2APB_DDRPHY_IPS_BASE_ADDR(0)
-binman_sym_declare(ulong, blob_ext_1, image_pos);
-binman_sym_declare(ulong, blob_ext_1, size);
+binman_sym_declare(ulong, ddr_1d_imem_fw, image_pos);
+binman_sym_declare(ulong, ddr_1d_imem_fw, size);
-binman_sym_declare(ulong, blob_ext_2, image_pos);
-binman_sym_declare(ulong, blob_ext_2, size);
+binman_sym_declare(ulong, ddr_1d_dmem_fw, image_pos);
+binman_sym_declare(ulong, ddr_1d_dmem_fw, size);
#if !IS_ENABLED(CONFIG_IMX8M_DDR3L)
-binman_sym_declare(ulong, blob_ext_3, image_pos);
-binman_sym_declare(ulong, blob_ext_3, size);
+binman_sym_declare(ulong, ddr_2d_imem_fw, image_pos);
+binman_sym_declare(ulong, ddr_2d_imem_fw, size);
-binman_sym_declare(ulong, blob_ext_4, image_pos);
-binman_sym_declare(ulong, blob_ext_4, size);
+binman_sym_declare(ulong, ddr_2d_dmem_fw, image_pos);
+binman_sym_declare(ulong, ddr_2d_dmem_fw, size);
#endif
/* We need PHY iMEM PHY is 32KB padded */
@@ -59,27 +59,27 @@ void ddr_load_train_firmware(enum fw_type type)
}
#endif
+ dmem_start = imem_start + imem_len;
+
if (CONFIG_IS_ENABLED(BINMAN_SYMBOLS)) {
switch (type) {
case FW_1D_IMAGE:
- imem_start = binman_sym(ulong, blob_ext_1, image_pos);
- imem_len = binman_sym(ulong, blob_ext_1, size);
- dmem_start = binman_sym(ulong, blob_ext_2, image_pos);
- dmem_len = binman_sym(ulong, blob_ext_2, size);
+ imem_start = binman_sym(ulong, ddr_1d_imem_fw, image_pos);
+ imem_len = binman_sym(ulong, ddr_1d_imem_fw, size);
+ dmem_start = binman_sym(ulong, ddr_1d_dmem_fw, image_pos);
+ dmem_len = binman_sym(ulong, ddr_1d_dmem_fw, size);
break;
case FW_2D_IMAGE:
#if !IS_ENABLED(CONFIG_IMX8M_DDR3L)
- imem_start = binman_sym(ulong, blob_ext_3, image_pos);
- imem_len = binman_sym(ulong, blob_ext_3, size);
- dmem_start = binman_sym(ulong, blob_ext_4, image_pos);
- dmem_len = binman_sym(ulong, blob_ext_4, size);
+ imem_start = binman_sym(ulong, ddr_1d_dmem_fw, image_pos);
+ imem_len = binman_sym(ulong, ddr_1d_dmem_fw, size);
+ dmem_start = binman_sym(ulong, ddr_2d_dmem_fw, image_pos);
+ dmem_len = binman_sym(ulong, ddr_2d_dmem_fw, size);
#endif
break;
}
}
- dmem_start = imem_start + imem_len;
-
pr_from32 = imem_start;
pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * IMEM_OFFSET_ADDR;
for (i = 0x0; i < imem_len; ) {
diff --git a/tools/binman/etype/section.py b/tools/binman/etype/section.py
index e3f362b442b8..bd67238b9199 100644
--- a/tools/binman/etype/section.py
+++ b/tools/binman/etype/section.py
@@ -875,7 +875,7 @@ def _CollectEntries(self, entries, entries_by_name, add_entry):
entries[entry.GetPath()] = entry
for entry in to_add.values():
self._CollectEntries(entries, entries_by_name, entry)
- entries_by_name[add_entry.name.replace('@', '-')] = add_entry
+ entries_by_name[add_entry.name] = add_entry
def MissingArgs(self, entry, missing):
"""Report a missing argument, if enabled
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