[PATCH 5/8] arch: arm: dts: HSD #1508104447-7: arm: dts: socfpga: stratix10: Add NAND u-boot.dtsi

[Jit Loon Lim]

From: Ley Foon Tan <ley.foon.tan at intel.com>

Add new file socfpga_stratix10_socdk_nand-u-boot.dtsi for Uboot specific
properties.

Signed-off-by: Ley Foon Tan <ley.foon.tan at intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim at intel.com>
---
 .../socfpga_stratix10_socdk_nand-u-boot.dtsi  | 36 +++++++++++++++++++
 1 file changed, 36 insertions(+)
 create mode 100644 arch/arm/dts/socfpga_stratix10_socdk_nand-u-boot.dtsi

diff --git a/arch/arm/dts/socfpga_stratix10_socdk_nand-u-boot.dtsi b/arch/arm/dts/socfpga_stratix10_socdk_nand-u-boot.dtsi
new file mode 100644
index 0000000000..5d8c3e2f91
--- /dev/null
+++ b/arch/arm/dts/socfpga_stratix10_socdk_nand-u-boot.dtsi
@@ -0,0 +1,36 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright Altera Corporation (C) 2020. All rights reserved.
+ */
+
+#include "socfpga_stratix10_socdk-u-boot.dtsi"
+
+/ {
+	chosen {
+		u-boot,boot0 = <&nand>;
+	};
+
+	memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		device_type = "memory";
+		/* 4GB */
+		reg = <0 0x00000000 0 0x80000000>,
+		      <1 0x80000000 0 0x80000000>;
+		u-boot,dm-pre-reloc;
+	};
+
+	soc {
+		eccmgr {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+	};
+};
+
+&nand {
+	u-boot,dm-pre-reloc;
+	nand-bus-width = <16>;
+};
-- 
2.26.2