[u-boot][PATCH 2/3] dt/bindings: memory: Add bindings for TI GPMC driver
Roger Quadros
rogerq at kernel.org
Wed Sep 28 14:11:48 CEST 2022
GPMC stands for General Purpose Memory Controller and it is
present on many Texas Instruments SoCs.
It supports a number of Asynchronous and Synchronous interfaces
and has various settings to configure the bus interface.
The DT bindings define all the various GPMC settings.
As the GPMC supports multiple devices on the bus, each
device is represented as a child and the respective
GPMC settings are situated there. (see ti,gpmc-child.yaml)
These binding docs are picked up from the Linux kernel.
Signed-off-by: Roger Quadros <rogerq at kernel.org>
---
.../memory/ti,gpmc-child.yaml | 252 ++++++++++++++++++
doc/device-tree-bindings/memory/ti,gpmc.yaml | 190 +++++++++++++
2 files changed, 442 insertions(+)
create mode 100644 doc/device-tree-bindings/memory/ti,gpmc-child.yaml
create mode 100644 doc/device-tree-bindings/memory/ti,gpmc.yaml
diff --git a/doc/device-tree-bindings/memory/ti,gpmc-child.yaml b/doc/device-tree-bindings/memory/ti,gpmc-child.yaml
new file mode 100644
index 0000000000..8e541acdb1
--- /dev/null
+++ b/doc/device-tree-bindings/memory/ti,gpmc-child.yaml
@@ -0,0 +1,252 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/memory-controllers/ti,gpmc-child.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: device tree bindings for children of the Texas Instruments GPMC
+
+maintainers:
+ - Tony Lindgren <tony at atomide.com>
+ - Roger Quadros <rogerq at kernel.org>
+
+description:
+ This binding is meant for the child nodes of the GPMC node. The node
+ represents any device connected to the GPMC bus. It may be a Flash chip,
+ RAM chip or Ethernet controller, etc. These properties are meant for
+ configuring the GPMC settings/timings and will accompany the bindings
+ supported by the respective device.
+
+properties:
+ reg: true
+
+# GPMC Timing properties for child nodes. All are optional and default to 0.
+ gpmc,sync-clk-ps:
+ description: Minimum clock period for synchronous mode
+ default: 0
+
+# Chip-select signal timings corresponding to GPMC_CONFIG2:
+ gpmc,cs-on-ns:
+ description: Assertion time
+ default: 0
+
+ gpmc,cs-rd-off-ns:
+ description: Read deassertion time
+ default: 0
+
+ gpmc,cs-wr-off-ns:
+ description: Write deassertion time
+ default: 0
+
+# ADV signal timings corresponding to GPMC_CONFIG3:
+ gpmc,adv-on-ns:
+ description: Assertion time
+ default: 0
+
+ gpmc,adv-rd-off-ns:
+ description: Read deassertion time
+ default: 0
+
+ gpmc,adv-wr-off-ns:
+ description: Write deassertion time
+ default: 0
+
+ gpmc,adv-aad-mux-on-ns:
+ description: Assertion time for AAD
+ default: 0
+
+ gpmc,adv-aad-mux-rd-off-ns:
+ description: Read deassertion time for AAD
+ default: 0
+
+ gpmc,adv-aad-mux-wr-off-ns:
+ description: Write deassertion time for AAD
+ default: 0
+
+# WE signals timings corresponding to GPMC_CONFIG4:
+ gpmc,we-on-ns:
+ description: Assertion time
+ default: 0
+
+ gpmc,we-off-ns:
+ description: Deassertion time
+ default: 0
+
+# OE signals timings corresponding to GPMC_CONFIG4:
+ gpmc,oe-on-ns:
+ description: Assertion time
+ default: 0
+
+ gpmc,oe-off-ns:
+ description: Deassertion time
+ default: 0
+
+ gpmc,oe-aad-mux-on-ns:
+ description: Assertion time for AAD
+ default: 0
+
+ gpmc,oe-aad-mux-off-ns:
+ description: Deassertion time for AAD
+ default: 0
+
+# Access time and cycle time timings (in nanoseconds) corresponding to
+# GPMC_CONFIG5:
+ gpmc,page-burst-access-ns:
+ description: Multiple access word delay
+ default: 0
+
+ gpmc,access-ns:
+ description: Start-cycle to first data valid delay
+ default: 0
+
+ gpmc,rd-cycle-ns:
+ description: Total read cycle time
+ default: 0
+
+ gpmc,wr-cycle-ns:
+ description: Total write cycle time
+ default: 0
+
+ gpmc,bus-turnaround-ns:
+ description: Turn-around time between successive accesses
+ default: 0
+
+ gpmc,cycle2cycle-delay-ns:
+ description: Delay between chip-select pulses
+ default: 0
+
+ gpmc,clk-activation-ns:
+ description: GPMC clock activation time
+ default: 0
+
+ gpmc,wait-monitoring-ns:
+ description: Start of wait monitoring with regard to valid data
+ default: 0
+
+# Boolean timing parameters. If property is present, parameter is enabled
+# otherwise disabled.
+ gpmc,adv-extra-delay:
+ description: ADV signal is delayed by half GPMC clock
+ type: boolean
+
+ gpmc,cs-extra-delay:
+ description: CS signal is delayed by half GPMC clock
+ type: boolean
+
+ gpmc,cycle2cycle-diffcsen:
+ description: |
+ Add "cycle2cycle-delay" between successive accesses
+ to a different CS
+ type: boolean
+
+ gpmc,cycle2cycle-samecsen:
+ description: |
+ Add "cycle2cycle-delay" between successive accesses
+ to the same CS
+ type: boolean
+
+ gpmc,oe-extra-delay:
+ description: OE signal is delayed by half GPMC clock
+ type: boolean
+
+ gpmc,we-extra-delay:
+ description: WE signal is delayed by half GPMC clock
+ type: boolean
+
+ gpmc,time-para-granularity:
+ description: Multiply all access times by 2
+ type: boolean
+
+# The following two properties are applicable only to OMAP3+ and AM335x:
+ gpmc,wr-access-ns:
+ description: |
+ In synchronous write mode, for single or
+ burst accesses, defines the number of
+ GPMC_FCLK cycles from start access time
+ to the GPMC_CLK rising edge used by the
+ memory device for the first data capture.
+ default: 0
+
+ gpmc,wr-data-mux-bus-ns:
+ description: |
+ In address-data multiplex mode, specifies
+ the time when the first data is driven on
+ the address-data bus.
+ default: 0
+
+# GPMC chip-select settings properties for child nodes. All are optional.
+ gpmc,burst-length:
+ description: Page/burst length.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 4, 8, 16]
+ default: 0
+
+ gpmc,burst-wrap:
+ description: Enables wrap bursting
+ type: boolean
+
+ gpmc,burst-read:
+ description: Enables read page/burst mode
+ type: boolean
+
+ gpmc,burst-write:
+ description: Enables write page/burst mode
+ type: boolean
+
+ gpmc,device-width:
+ description: |
+ Total width of device(s) connected to a GPMC
+ chip-select in bytes. The GPMC supports 8-bit
+ and 16-bit devices and so this property must be
+ 1 or 2.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [1, 2]
+ default: 1
+
+ gpmc,mux-add-data:
+ description: |
+ Address and data multiplexing configuration.
+ Valid values are
+ 0 for Non multiplexed mode
+ 1 for address-address-data multiplexing mode and
+ 2 for address-data multiplexing mode.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 1, 2]
+
+ gpmc,sync-read:
+ description: |
+ Enables synchronous read. Defaults to asynchronous
+ is this is not set.
+ type: boolean
+
+ gpmc,sync-write:
+ description: |
+ Enables synchronous writes. Defaults to asynchronous
+ is this is not set.
+ type: boolean
+
+ gpmc,wait-pin:
+ description: |
+ Wait-pin used by client. Must be less than "gpmc,num-waitpins".
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+ gpmc,wait-pin-polarity:
+ description: |
+ Set the desired polarity for the selected wait pin.
+ 0 for active low, 1 for active high.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 1]
+
+ gpmc,wait-on-read:
+ description: Enables wait monitoring on reads.
+ type: boolean
+
+ gpmc,wait-on-write:
+ description: Enables wait monitoring on writes.
+ type: boolean
+
+required:
+ - reg
+
+# the GPMC child will have its own native properties
+additionalProperties: true
diff --git a/doc/device-tree-bindings/memory/ti,gpmc.yaml b/doc/device-tree-bindings/memory/ti,gpmc.yaml
new file mode 100644
index 0000000000..e188a4bf75
--- /dev/null
+++ b/doc/device-tree-bindings/memory/ti,gpmc.yaml
@@ -0,0 +1,190 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/memory-controllers/ti,gpmc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Texas Instruments GPMC Memory Controller device-tree bindings
+
+maintainers:
+ - Tony Lindgren <tony at atomide.com>
+ - Roger Quadros <rogerq at kernel.org>
+
+description:
+ The GPMC is a unified memory controller dedicated for interfacing
+ with external memory devices like
+ - Asynchronous SRAM-like memories and ASICs
+ - Asynchronous, synchronous, and page mode burst NOR flash
+ - NAND flash
+ - Pseudo-SRAM devices
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - ti,am3352-gpmc
+ - ti,am64-gpmc
+ - ti,omap2420-gpmc
+ - ti,omap2430-gpmc
+ - ti,omap3430-gpmc
+ - ti,omap4430-gpmc
+
+ reg:
+ minItems: 1
+ maxItems: 2
+
+ reg-names:
+ items:
+ - const: cfg
+ - const: data
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+ description: |
+ Functional clock. Used for bus timing calculations and
+ GPMC configuration.
+
+ clock-names:
+ items:
+ - const: fck
+
+ power-domains:
+ maxItems: 1
+
+ dmas:
+ items:
+ - description: DMA channel for GPMC NAND prefetch
+
+ dma-names:
+ items:
+ - const: rxtx
+
+ "#address-cells": true
+
+ "#size-cells": true
+
+ gpmc,num-cs:
+ description: maximum number of supported chip-select lines.
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+ gpmc,num-waitpins:
+ description: maximum number of supported wait pins.
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+ ranges:
+ minItems: 1
+ description: |
+ Must be set up to reflect the memory layout with four
+ integer values for each chip-select line in use,
+ <cs-number> 0 <physical address of mapping> <size>
+ items:
+ - description: NAND bank 0
+ - description: NOR/SRAM bank 0
+ - description: NOR/SRAM bank 1
+
+ '#interrupt-cells':
+ const: 2
+
+ interrupt-controller:
+ description: |
+ The GPMC driver implements and interrupt controller for
+ the NAND events "fifoevent" and "termcount" plus the
+ rising/falling edges on the GPMC_WAIT pins.
+ The interrupt number mapping is as follows
+ 0 - NAND_fifoevent
+ 1 - NAND_termcount
+ 2 - GPMC_WAIT0 pin edge
+ 3 - GPMC_WAIT1 pin edge, and so on.
+
+ '#gpio-cells':
+ const: 2
+
+ gpio-controller:
+ description: |
+ The GPMC driver implements a GPIO controller for the
+ GPMC WAIT pins that can be used as general purpose inputs.
+ 0 maps to GPMC_WAIT0 pin.
+
+ ti,hwmods:
+ description:
+ Name of the HWMOD associated with GPMC. This is for legacy
+ omap2/3 platforms only.
+ $ref: /schemas/types.yaml#/definitions/string
+ deprecated: true
+
+ ti,no-idle-on-init:
+ description:
+ Prevent idling the module at init. This is for legacy omap2/3
+ platforms only.
+ type: boolean
+ deprecated: true
+
+patternProperties:
+ "@[0-7],[a-f0-9]+$":
+ type: object
+ description: |
+ The child device node represents the device connected to the GPMC
+ bus. The device can be a NAND chip, SRAM device, NOR device
+ or an ASIC.
+ $ref: "ti,gpmc-child.yaml"
+
+
+required:
+ - compatible
+ - reg
+ - gpmc,num-cs
+ - gpmc,num-waitpins
+ - "#address-cells"
+ - "#size-cells"
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: ti,am64-gpmc
+ then:
+ required:
+ - reg-names
+ - power-domains
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/gpio/gpio.h>
+
+ gpmc: memory-controller at 50000000 {
+ compatible = "ti,am3352-gpmc";
+ reg = <0x50000000 0x2000>;
+ interrupts = <100>;
+ clocks = <&l3s_clkctrl>;
+ clock-names = "fck";
+ dmas = <&edma 52 0>;
+ dma-names = "rxtx";
+ gpmc,num-cs = <8>;
+ gpmc,num-waitpins = <2>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges = <0 0 0x08000000 0x10000000>; /* CS0 @addr 0x8000000, size 0x10000000 */
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ nand at 0,0 {
+ compatible = "ti,omap2-nand";
+ reg = <0 0 4>;
+ interrupt-parent = <&gpmc>;
+ interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
+ <1 IRQ_TYPE_NONE>; /* termcount */
+ ti,nand-xfer-type = "prefetch-dma";
+ ti,nand-ecc-opt = "bch16";
+ ti,elm-id = <&elm>;
+ rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */
+ };
+ };
--
2.17.1
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