[RESEND PATCH 2/3] imx6: clock: add support to get LCD pixel clock rate
Dario Binacchi
dario.binacchi at amarulasolutions.com
Sat Apr 22 16:11:18 CEST 2023
Add the get_lcd_clk() function to get the LCD pixel clock rate.
The patch has been tested on imx6ul platform.
Signed-off-by: Dario Binacchi <dario.binacchi at amarulasolutions.com>
---
arch/arm/include/asm/arch-mx6/clock.h | 2 +
arch/arm/mach-imx/mx6/clock.c | 58 +++++++++++++++++++++++++++
2 files changed, 60 insertions(+)
diff --git a/arch/arm/include/asm/arch-mx6/clock.h b/arch/arm/include/asm/arch-mx6/clock.h
index 8ae49715789c..81af89c631f5 100644
--- a/arch/arm/include/asm/arch-mx6/clock.h
+++ b/arch/arm/include/asm/arch-mx6/clock.h
@@ -41,6 +41,8 @@ enum mxc_clock {
MXC_SATA_CLK,
MXC_NFC_CLK,
MXC_I2C_CLK,
+ MXC_LCDIF1_CLK,
+ MXC_LCDIF2_CLK,
};
enum ldb_di_clock {
diff --git a/arch/arm/mach-imx/mx6/clock.c b/arch/arm/mach-imx/mx6/clock.c
index 17d8dcd5c841..267d86ab4194 100644
--- a/arch/arm/mach-imx/mx6/clock.c
+++ b/arch/arm/mach-imx/mx6/clock.c
@@ -418,6 +418,60 @@ static u32 get_uart_clk(void)
return freq / (uart_podf + 1);
}
+static u32 get_lcd_clk(unsigned int ifnum)
+{
+ u32 pll_rate;
+ u32 pred, postd;
+
+ if (!is_mx6sx() && !is_mx6ul() && !is_mx6ull() && !is_mx6sl() &&
+ !is_mx6sll()) {
+ debug("This chip does't support lcd\n");
+ return 0;
+ }
+
+ pll_rate = decode_pll(PLL_VIDEO, MXC_HCLK);
+ if (ifnum == 1) {
+ if (!is_mx6sl()) {
+ pred = __raw_readl(&imx_ccm->cscdr2);
+ pred &= MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_MASK;
+ pred = pred >> MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_OFFSET;
+
+ postd = readl(&imx_ccm->cbcmr);
+ postd &= MXC_CCM_CBCMR_LCDIF1_PODF_MASK;
+ postd = postd >> MXC_CCM_CBCMR_LCDIF1_PODF_OFFSET;
+ } else {
+ pred = __raw_readl(&imx_ccm->cscdr2);
+ pred &= MXC_CCM_CSCDR2_LCDIF_PIX_PRE_DIV_MASK;
+ pred = pred >> MXC_CCM_CSCDR2_LCDIF_PIX_PRE_DIV_OFFSET;
+
+ postd = readl(&imx_ccm->cscmr1);
+ postd &= MXC_CCM_CSCMR1_LCDIF_PIX_PODF_OFFSET;
+ postd = postd >> MXC_CCM_CBCMR_LCDIF1_PODF_OFFSET;
+ }
+ } else if (ifnum == 2) {
+ if (is_mx6sx()) {
+ pred = __raw_readl(&imx_ccm->cscdr2);
+ pred &= MXC_CCM_CSCDR2_LCDIF2_PRE_DIV_MASK;
+ pred = pred >> MXC_CCM_CSCDR2_LCDIF2_PRE_DIV_OFFSET;
+
+ postd = readl(&imx_ccm->cscmr1);
+ postd &= MXC_CCM_CSCMR1_LCDIF2_PODF_MASK;
+ postd = postd >> MXC_CCM_CSCMR1_LCDIF2_PODF_OFFSET;
+
+ } else {
+ goto if_err;
+ }
+ } else {
+ goto if_err;
+ }
+
+ return DIV_ROUND_UP_ULL((u64)pll_rate, (postd + 1) * (pred + 1));
+
+if_err:
+ debug("This chip not support lcd iterface %d\n", ifnum);
+ return 0;
+}
+
static u32 get_cspi_clk(void)
{
u32 reg, cspi_podf;
@@ -1273,6 +1327,10 @@ unsigned int mxc_get_clock(enum mxc_clock clk)
return get_usdhc_clk(3);
case MXC_SATA_CLK:
return get_ahb_clk();
+ case MXC_LCDIF1_CLK:
+ return get_lcd_clk(1);
+ case MXC_LCDIF2_CLK:
+ return get_lcd_clk(2);
default:
printf("Unsupported MXC CLK: %d\n", clk);
break;
--
2.32.0
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